I'm attempting to use the NIOS-II socket server example on a Cyclone V with Quartus 18.0 standard. The example hardware uses the regular scatter gather DMA but when I create the NIOS-II project, the compile errors seem to indicate it wants the modular scatter-gather DMA.
So I'm trying to change the hardware to use the Modular Scatter-Gather DMA. But QSYS is giving the errors shown in the attached image and below:
Error: q_sys.eth_tse.receive/dma_rx.st_sink: The source has a startofpacket signal of 1 bits, but the sink does not.
Error: q_sys.eth_tse.receive/dma_rx.st_sink: The source has a endofpacket signal of 1 bits, but the sink does not.
Error: q_sys.dma_tx.st_source/eth_tse.transmit: The sink has a startofpacket signal of 1 bits, but the source does not.
Error: q_sys.dma_tx.st_source/eth_tse.transmit: The sink has a endofpacket signal of 1 bits, but the source does not.
Am I connecting the Modular Scatter-Gather DMA correctly? It looks to me like it does not need separate onchip RAM for the descriptors.
Hi,
The Avalon ST interface is sending data in the packet (with SOP and EOP signal), in this case, you have to enable the "Packet Support Enable" option in the Modular Scatter Gather DMA IP.
Regards -SK
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Hi,
The Avalon ST interface is sending data in the packet (with SOP and EOP signal), in this case, you have to enable the "Packet Support Enable" option in the Modular Scatter Gather DMA IP.
Regards -SK
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Hello @BIdro ,
I'm afraid we abandoned the NIOS II years ago (ok tools but way too slow) and Altera SoC (nonsensical tools) and I don't really remember exactly what I did. But I think I took the standard simple socket server example project and enabled "Packet Support Enable" as suggested by the moderator.
Thanks
