Jtag debug problem... any suggestion welcome.....

[Altera_Forum]

I'm working on my board designed with NiosII and Ep1C20 device, extarnal 16 bit flash and 32 bit dram. 

I check the tco e tsu for pll shift dram clock, from timing analyzer will be work at 100Mhz with -2.5 nS shift. The port jtag is working during fpga configuration and also with "custom hardware" for flash programmer tools, where with jtag port i can program nios application and fpga configuration file with success without any problem. When i try to run the debug the system fail to connect, with the message :  There are no Nios II CPUs with debug modules available which match the values specified. Please check that your PLD is correctly configured, downloading a new SOF file if necessary.  do you have any suggestion or item to ceck ?  regards  Roberto

[Altera_Forum]

I have to ask.... you added an OCI core to your system right (in the Nios II settings) 

 Also you are programming the correct hardware right? (if you are downloading/debuging software immediately after Flash programming, you may have the flash programmer hardware still in the FPGA <-- I&#39;m assuming you are using the IDE for flash programming)  Usually bringing up new systems I start small (CPU, onchip memory, JTAG Uart, SystemID, etc...) then add in more components so that I&#39;m not debugging 10+ components at once.

[Altera_Forum]

Yesss, i have programmed the flash with flash programmer inside the IDE and HW custom project as target. 

If there are not other way to understan the origin of problem i will follow your suggestion , a restricted design with only the nios core, flash interface and onchip memory............ http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif

[Altera_Forum]

I try to realize a smal project with sram block inside ad minimum requirements, i choose internal ram as target in IDE library properties but the result is the same..... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif  

 roby

[Altera_Forum]

The problem was solved, a small capacitor (100 pF) from Jtag clock and ground solve the bug. I think this is do to some glich or noise, i don&#39;t like this type of solution , is not "clean" but is the only one that i found. I&#39;m using the USB blaster Rev.B my be a problem of ICE jtag, on my board i have only the port connected to fpga with short trace. 

Note that only in uart jtag mode we see the problem, not during fpga loading and not during flash programming with the tools inside the IDE. ( it use jtag uart also ???), my be legated to different signal speed in jtag, in any case this interface is very critical.  Roby

[Altera_Forum]

There are also some proposals from Altera application engineer  

that sometimes a small series resistor (about 32ohms) in DCLK helps , so placing a R-C combination in layout is a good idea.

[Altera_Forum]

Thanxs a lot lads, I have been stucked with this one as well for a week http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif .

[Altera_Forum]

i spent also a lto of time for this problem, the strange thing is that was working with fpga loading and flash programmer, but not on uart jtag usage. The series resistor my be fine also, in any case this interface is too much criitical......... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif  

 roby