Hi, i am trying to ake use of OC Pci Bridge on my designe, and finallyi could make it work as i want. I can master the network and receive/send bursts of data on Linux. But i need a sugestion now. I need totransfer some data to computer, and to tell it when the transfer isdone i will generate a interrupt. My question is.. when i finishtransfer data from my wishbone master to the slave at the bridge, itdoes not mean that all the data was transfered to the computer.. sohow can i know when all the data is at the computer's memory, so i cangenerate the interrupt?Actually, i think that would be a general problem on any assinchrounous Bridge interface.Thank you, let me know if i was not enough clear.
