Nios V uC/TCP IP Failed

[JLee25]

Hi support,

  I am learning the simple socket server design on Cyclone 10 GX.

For unknown reason, the initialization process stopped with the error code (2010),

It's the TSE with DP83848.

The signals on MDIO and MDC is working.

Therefore I would like to know how to debug this issue.

Thank you.

BRs,

Johnson

[EBERLAZARE_I_Intel]

Hi,

This case just got routed to me today.

May I know your setup? Are you directly connecting the board to your PC? If yes, then you may need to disable the "DHCP feature (!DEF_TRUE)":

https://www.intel.com/content/www/us/en/docs/programmable/726952/23-4/configuring-mac-and-ip-addresses.html

Once you have set your IP address etc, rebuild the application and re-program the new .hex/.elf whichever you were using.

[JLee25]

Hello,

  It's a custom board with C10 GX and DP83848.

We use Nios II with NicheStack in the past and are porting the Niso V now.

So the Hareware should be fine.

The qsys connection is like below.

The Nos V is running on EMIF.

Following your instruction, the socket is running now.

But I can not connect to the server and ping to the specific is not responding..

Form the STP, the ff_rx_a_full is always high.

I think there are problems on the FPGA side since the TSE IP is not responding..

BRs,

Johnson

[EBERLAZARE_I_Intel]

Hi,

Okay, we are moving in the correct direction, at least we can see what we can do next.

With the addresses now configure properly, and that the message “[sss_task] Simple Socket Server listening on port

<port number>” is displayed when the µC/TCP-IP Stack is ready for connection.

Can you show/screenshot on your Host PC's CMD, running below steps?:

After the µC/TCP-IP Stack is ready, you can start a telnet session to interact with the stack.

To start a telnet session, follow these steps:

1. From your operating system, open a command shell or a terminal.

Note: On Windows, you can also use Run on the Start menu.

2. Type the following command, specifying either the static IP address or the DHCPserver-provided IP address:

telnet <IP Address> <Port>

telnet 192.168.1.110 80

[JLee25]

Hi,

  I tried telnet and ping command.

But no reply from the server

[EBERLAZARE_I_Intel]

Hi,

How is your setup? Does your computer (that is connected to the board) connected to a VPN or secure connection?

[JLee25]

Hi Eberlazare,

  No, just through a switch.

And I am debugging the qsys..

I can see the mii_rx_d to TSE.

But for unknown reason, the ff_rx_a_full going high and ff_rx_rdy goes low after the SSS starting.

[JLee25]

Hi,

  I think the problem is the TSE not responding for unknown reason after the SSS running...

I STP the signals between TSE RX and the RX MSGDMA.

The ff_rx_rdy going low and not returned to high.

Perhaps something wrong on my Qsys setting or..

I feel the MSGDMA is not working and there's not much data about this IP..

I upload the QAR file for your analysis.

Thank you.

[JLee25]

Hi，

  Please use the attached QAR for analysis.

Thank you.

[EBERLAZARE_I_Intel]

Hi,

Thanks, I will check out the design.

[EBERLAZARE_I_Intel]

Hi,

What is the Quartus version that you are working on?

[JLee25]

I am using Quartus Prime Pro 23.2.0 in Win 10.

Thank you.

[EBERLAZARE_I_Intel]

Hi,

I may need some days to debug this issue, I shall update to you again in the next few days.

[EBERLAZARE_I_Intel]

Hi,

From my findings, the signal issue you mentioned, it seems that it has something to do with some settings that need to be tweaked.

I will further investigate towards that and get back to you soon with some suggested workaround.

Thanks for your patience.

[EBERLAZARE_I_Intel]

Hi,

Does the issue always have the "ff_rx_rdy" high? OR do you have it work at random times?

One of the workaround I could find was implementing a reset. I am not that familiar with the TSE IP, you could try to perform a reset signal:

https://www.intel.com/content/www/us/en/docs/programmable/683402/22-4-21-1-0/clock-and-reset-signals.html

[JLee25]

Hi,

  From the STP content below, I think the ff_rx_rdy is a signal from DMA.

After downloading the sof and elf, the system booted with ff_rx_rdy high, which indicate to the core ready to receive data.

But it went low after with the network connected.. 

Therefore I guess there are problems on the msgdma ..

I read back some register settings on TSE core, and thought it should be configured correctly.

[JLee25]

Hi,

  I modify the design with Nios V to EMIF through a memory mapped clock crossing bridge and DMA through another bridge.

But for unknown reason the DMA bridge is not running...

I STP the bus and found only Nios V is running..

Any suggestions ? DMA driver or ...

[EBERLAZARE_I_Intel]

Hi,

Is the DMA & EMIF visible in the "drivers" tab in BSP-editor?

[JLee25]

Hi,

  I believe so, as

and

[EBERLAZARE_I_Intel]

Hi,

Since we currently do not have the example for the Simple Socket Server with EMIF for Nios V, can you try with the OCRAM as per the Nios V handbook?:

https://www.intel.com/content/www/us/en/docs/programmable/726952/23-4/processor-using-the-microc-tcp-ip-stack.html

Try with OCRAM, if it works then I can recommend to try with EMIF.

[JLee25]

Hi,

  I tried OCRMA before EMIF and it's not working for unknown reason.

I upload the QAR for your reference.

The STP content is the same as EMIF...

Perhaps some components are with wrong settings..