Problem to add an off chip SSRAM

[Altera_Forum]

Hello, 

 I have a problem when I want to add an off chip memory in my design. I have read a lot about this issue but I have not been able to find the solution to my problem. Let me explain it into more details...  I am currently doing a project for my master degree and I use the last available version of Quartus II (11.1). I am new using this version and my first design was to create a Nios in order to receive some data for the usart and to set (or clear) several leds depending on the data. I used an on chip memory and everything was ok! My second design was the same but using the off chip SSRAM intregrated on the board which I use. I tend to use Quartus 6.0 at work and I always use this off chip memory. Therefore, I copied the design but it does not work in the last version of Quartus II. When I click on Run As... in the NIOS II EDS I get the following error:  [target connection]: connected system id hash not found on target at expected base address.  If I click on mismatch system ID the error is that the .ELF cannot be downloaded. I am very confused because the design and the connections are exactly the same than I use at work. I have been able to read that this error is because of a problem with the reset or clock. I do not know if it will be the problem but in my symbol created for SOPC Builder I have a reset signal in the SSRAM controller. With Quartus II 6.0 I never got that signal and in the user guide of the board does not appear the pin where I have to connect this signal so I have not connected it.   I cannot attach my project (it takes up too much). I attach a picture about my symbol and the SOPC Builder design.  By the way, I would like to mention a difference between version 6.0 and 11.1. When I go to pin planner in the version 6.0 I see the pins which I have added in the design. By contrast, in pin planner of the version 11.1 I can only see the pins which appears in the SOPC Builder symbol and if I add a new pin, it does not appear. Is it normal? I would like to have the pin planner like the version 6.0, it is more comfortable for me but I do not know what option has to be changed to get it.  I will be completely delighted for any help. Many thanks and happy new year everybody!!!

[Altera_Forum]

Floating reset_n signal is probably left at GND or removed during synthesis, so Your SSRAM controller is either in reset or optimized out. 

 NEVER KEEP RESET PIN FLOATING! And it is usually a bad technique to connect it to VCC or GND signals, since those can be also optimized out.

[Altera_Forum]

First of all, many thanks for your help :) 

 As for your message, I tie the global reset signal to VCC, but the SSRAM reset signal I do not know where I have to connect it.   In the SSRAM section of the user guide, there is not any reset pin. In fact, with Quartus II 6.0 the SSRAM reset signal does not appear in SOPC symbol and everything works well. Where should I connect this signal in Quartus II 11.1?  Anyway, there are signals such as ssram_adv_n or ssram_adsp_n which do not appear in the SOPC symbol. I would like to tie them to VCC like in my design with Quartus II 6.0, but with the version 11.1 I am unable to do it because they do not appear in pin planner even thought I define pins with those names. How could I solve this issue?  Any tip is welcome ;) Sorry if my problem is quite basic but I am not used to working with the last version of Quartus II. Many thanks!

[Altera_Forum]

By the way, here is a link with the user guide of my board for if it is helpul: 

 http://www.altera.com/literature/manual/mnl_nios2_board_cycloneii_2c35.pdf

[Altera_Forum]

1. Tie that reset_n pin to VCC (same as global reset). 

2. Create output ports and connect them to required SSRAM pins. Tie those ports to required level.

[Altera_Forum]

Many thanks Socrates for your help again :) 

 I will try what you told me in your message but note global reset is an input pin and SSRAM reset is an output pin so I am not sure if it will work.  I will write when I have checked your changes ;)

[Altera_Forum]

Oh, my bad, it's really output! Then leave it unconnected.

[Altera_Forum]

Yes, but I had unconnected the SSRAM reset and it did not work. Do you have any new idea about what the problem can be?

[Altera_Forum]

Check it's state with signaltap. It should be released when the memory controller is configured.

[Altera_Forum]

I have already solved the problem. I was unable to modify pin planner because of the fact that I created new pins and they did not appear in pin planner :confused: 

 I could only see the pins of my SOPC symbol and so I could not add the adsp and adv pins of SSRAM which are not in the SOPC symbol. I deleted my project and created another one. The only difference was that I named the .bdf with the same name as the project (in the previous project the names are different) and it seems have solved the problem because I can modify pin planner with no problems. I have added the adsp and adv pins and everything works well :)   The SSRAM reset is not connected, it did not affected to the design because, as I had mentioned before, the board which I use does not have pin for SSRAM reset.   Anyway, I am very grateful to you for your quick help. Many thanks ;)