Problems when running from SRAM

[Altera_Forum]

Hi All, 

 First of all lets introduce me.  I'm a PhD student, and recently I have received two NiosII development kits, a Cyclone Edition and a Stratix Pro Edition.  I have some experience in Embedded design, but just with Xilinx FPGAs and tools. It's my first contact with Altera's world.  I have some questions, and I will be very thankful if someone could give me some answers.  1- In the SDRAM pinout list of my board, the clk pin says: U2, pin 19. A comment says that this pin is buffered from Stratix pin clock-output E15. I can't understand this. To wich pin I have to send a clk signal? What means U2, pin 19? I have generated a clk signal with a PLL and connected it to pin E15 (I take it from an example included in the kit), and SDRAM works OK, but I would be very happy if I know I am doing it all right.  2- I have generated a system with a Nios2, UART, on chip memory (64Kb), sram, and sdram. Running a program from on-chip memory I have tested that both sram, and sdram works all right (doing some memory writes and looking to memory with the debugger to se if the values were written OK). But when I try to run a simple "Hello World" program I can't run it from SRAM. The IDE downloads the program but nothing is showed in the UART output. Running it from on-chip memory or from SDRAM works all right. Any ideas about what is going wrong when running the program from SRAM?  3- In the example provided with the kit, I have seen that it has a peripheral called "reconfig_request_pio", and its output is connected to pin U2 (the same pin that board docs says that is clk pin of SDRAM). What means that? Wich is the function of this peripheral? Why is connected to pin U2?  and last question:  4- When doing te pin assigments to the external bus to wich SRAM is connected, I have connected all data pins as are in the documentation, but when synthesizing an error message says that ~DATA0~ can't be connected to pin H12 because sram_data[0] is connected to it. What in the hell is the ~DATA0~ signal? If I delete the assigment to sram_data[0], it synthesizes all right, and it seems that the SRAM works (doing writes and reads), but I can't run programs from SRAM as mentioned in question 1.   That's all, I know it's a large post, so excuse me if it's too boring.  Best regards,  Pablo H.

[Altera_Forum]

Hi again, just after writing the post I realized that the memory tests I was doing to the sram were not correct at all. All the values written to memory had a '1' in the less significant bit. I have tested writting values with a '0' at the LSB and it does not work (there is always a '1' in the LSB). So pin sram_data[0] is not connected (I remove it from the pin assigment list because the conflict with the ~DATA0~ signal) or it is asserted to '1'. 

 What in the hell is ~DATA0~ signal???  Best regards,  Pablo H.

[Altera_Forum]

Pablo, 

 It&#39;s probably best to start by using one of the design examples for your board(s). You can find them in: <nios2_root>/examples/[verilog|vhdl]/<board_name>.  You can also use your design example of choice as the starting point for whatever you&#39;d like to design.  Also, for testing memory, I would recommend using the "Memory Test" software example.  - slacker

[Altera_Forum]

DATA0 is a dedicated pin for FPGA configration. You can look up the Statix or Cyclone Handbook.pdf.

[Altera_Forum]

Hi all, 

 I have solved the problem with ~DATA0~  The solution was:  In the settings menu, in "Device & Pin Options", under the "Dual-Purpose Pins" tab set Data[0] to be "Use as regular I/O".  Best regards,  Pablo H.