Question about Nios2 Min system.

[Altera_Forum]

Hello, 

I do Nios2 min system with Nios2(NiosII/s with jtag debug module level 1) + OnChipRam + Uart. But something warning occur in sopc builder. Besides warning, I also have some question.  (1) In sopc, I make my system with NisII/s + 4k OnChipRam + Uart0, there has a warning: cpu: The reset address points to volatile memory. Execution of undefined code may occur upon reset.  (Q1) I don't know the warning mean, and how to correct.  (2) There is jtag_debug_module in NiosII, which Nios has not.   (Q2) I want to know if jtag_debug_module is used for NiosII IDE, and what different bwteen uart and jtag_debug_module in using.  (3) Nios uses cygwin as software development, but when I compile .c file (nb filename.c) under sopc builder4.1 cygwin, it says that nios-elf-gcc: Command not found. But I have installed the nios-elf-gcc tools of NiosII.  (Q3) What is the problem? If environment variable is wrong, or I must set the path, how to do.  Thank you.

[Altera_Forum]

A1. Your memory is a RAM, and you (well it did this by default) have your reset address in that RAM. So when you power up the contents of that RAM will be undefined (volatile memory). But don't worry about that, you probably want to be able to download your code into that memory (you might want more memory though like 64k for example). Also since you are familiar with NIOS I, I recommend you avoid all the legacy stuff like the GERMS monitor, sdk, building from the cygwin prompt. Another thing you should know is to bypass the data cache you have to use IORD and IOWR macro calls or set bit 31 of the address to '1' to do the bypass (declaring volatile pointers does not do the bypass for you anymore, but with HAL you shouldn't need to do this anyway). 

 A2. Yes it is used by the NIOS II IDE (used with a few other things as well). The "JTAG UART" is the same thing as the "UART" (RS232) only over jtag. The Debug module allows you communicate with the NIOS II core over JTAG, debug, and download your code (so I think that is all you will need).  A3. nb (Nios Build) was for NIOS I. I recommend using the NIOS II IDE since the new HAL and interface is pretty nice (I hated it at first but after a few days I got over it and realized it was a much improved method to coding). NIOS II is project based so I recommend you read this: http://www.altera.com/literature/hb/nios2/...n2sw_nii5v2.pdf (http://www.altera.com/literature/hb/nios2/n2sw_nii5v2.pdf) (up to page 92 will give you the basics and how to use HAL (Hardware Abstraction Layer)).   As a side note, I also recommend opening a sample reference design just to see how everything is set up (the hardware changes between NIOS I and NIOS II from the interface level are small, but the software side is almost completely new).  If you have more questions let us know and someone here will get back to you.  Cheers.

[Altera_Forum]

Thank you! 

 If I have question about nios, I will ask someone in the forum.  But there said in your reply that    "Another thing you should know is to bypass the data cache you have to use IORD and IOWR macro calls or set bit 31 of the address to '1' to do the bypass (declaring volatile pointers does not do the bypass for you anymore, but with HAL you shouldn't need to do this anyway)."  I don't know it clearly. Can you give something described this or others.

[Altera_Forum]

Heekee, 

 Don't worry about the dcache bypass for now (dcashe is only in the f core). You are using the s core, so it should work fine.    Stefaan

[Altera_Forum]

Sorry about that, I didn't notice which core you are using. 

 In case you move up to the 'f' core here's my second shot:  In Nios I (the first one from years back), when you had data cache available in the system in order for your data to bypass the cache all you did was declare your register pointers to be volatile. The keyword volatile tells the compiler to not synthesize out the variable if it believes it can along with bypassing the cache (like if you keep reading from an external register the compiler will think that's pretty dumb and optimize all the other reads because you already should have the data). Bypassing the cache prevents a similar problem where you perform one access to that register, it become stored in the cache then each time you go to read from it again, if it is still in cache then it will read the value from cache and not the register (so it'll look like the register never changes value).  In Nios II volatile is now in the pure form, meaning that it will not sythesize the variable away but it no longer bypasses the cache for you. It's still a good idea to declare your pointers with volatile to make sure they don't disappear after the compile, but you now have to use IORD and IOWR which are macros that set bit 31 for you (hardware sees that bit high and knows to read from memory and not cache).  Hope that clarifies what I tried to say before.