Running Altera Nios2 Multiprocessor Tutorial

[Altera_Forum]

Hello all, 

 Has anyone had any luck running Altera's Multiproc tutorial.  I have tried several times on different machines with no success.  I am running the Standard project for the Altera Cyclone II dev kit. I am using Quartus 5.1 with Nios II 5.1.  I am able to step through the debugger, which is good, but in code it seems to be stuck without the CPU 1 ID being recognized.  Any thoughts?  Thanks,  -Baycool

[Altera_Forum]

Hi, 

 I had no problems in running the multiprocessor tutorial...  can you please be more specific about your problem?  ...about the CPU 1 ID... when you debug, you can find the CPU ID in the register window of the debugger... what are the values for the three CPUs?  bye  Paolo

[Altera_Forum]

Hello Paolo, 

 I am able to step through messages being sent in debug mode, but not in run mode. Not sure what is causing this yet.  However, the tutorial has the potential for a bug.  When you build the system you are building the comm for CPU 1. The comm code in the multi.c is for cpuid =1. Now , I think this is normally the case as SOPC will assign cpuid = 0( you later add "1" in code). However, in the tutorial my cpu 1 is assigned a cpuid = 0x2. I looked back over the tutorial, and this value is assigned by system. I am not sure how system makes this assignement but it is not based, I believe on the names of the cpu in SOPC. This is where the potential for the bug lies.If you follow the tutorial you connect your JTAG UART to cpu1 assuming that the system will assign cpu1= 0x0. if the system assigns another value to this register then you have a problem  Now normally if the system assigns values the expected way: cpu1 = 0x0 cpu2 = 0x1 cpu3= 0x2  there is no problem.  As a test of my theory I went back and reconnected my cpu2 to JTAG UART and as expected I was able to in debug mode pass thorugh the code that sends messages. I am still unable to do this in run mode, not quite sure.  Thanks,  -Ray

[Altera_Forum]

--- Quote Start ---  originally posted by baycool@Jan 10 2006, 03:57 AM i am able to step through messages being sent in debug mode, but not in run mode. not sure what is causing this yet. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12079)  --- quote end ---    --- Quote End ---    That&#39;s quite strange... I don&#39;t think it is related to the fact that the system is a multiprocessor, because the JTAG Uart does not rely on the fact you are using a multiprocessor... but just hooks on the JTAG chain... I never had a problem like that...    --- Quote Start ---  originally posted by baycool@Jan 10 2006, 03:57 AM however, the tutorial has the potential for a bug.  when you build the system you are building the comm for cpu 1. the comm code in the multi.c is for cpuid =1. now , i think this is normally the case as sopc will assign cpuid = 0( you later add "1" in code). however, in the tutorial my cpu 1 is assigned a cpuid = 0x2. i looked back over the tutorial, and this value is assigned by system. i am not sure how system makes this assignement but it is not based, i believe on the names of the cpu in sopc. this is where the potential for the bug lies.if you follow the tutorial you connect your jtag uart to cpu1 assuming that the system will assign cpu1= 0x0. if the system assigns another value to this register then you have a problem  now normally if the system assigns values the expected way: cpu1 = 0x0 cpu2 = 0x1 cpu3= 0x2  there is no problem.  as a test of my theory i went back and reconnected my cpu2 to jtag uart and as expected i was able to in debug mode pass thorugh the code that sends messages. i am still unable to do this in run mode, not quite sure. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12079)  --- quote end ---    --- Quote End ---    I think the problem you are pointing out is strictly related to the way SOPCBuilder assigns the CPUID to Nios II processors.  We found that problem a few months ago (at that time it caused me a few headaches... look at values this post on the cpuid values here (http://forum.niosforum.com/forum/index.php?showtopic=1060&hl=)) while implementing the Multiprocessor Startup Barrier for ERIKA Enterprise.  Until Nios II 5.1 there was not an official position on the ways CPUIDs are assigned. The workaround we found is just to... look at the PTF and try :-) ... Basically there are a few things to look at...a description of them can be found on the ERIKA Enterprise Manual, page 111 (available for free at the erika enterprise literature page (http://www.evidence.eu.com/nios2/literature.asp)).  The best thing IMHO would have been either to be able to assign the CPUID values directly, or to have a combo box in the Mutex component.  In any case, the problems seems to be solved in Nios II 5.1 where it is clearly stated in a subnote of the Mutex Component (open SOPCBuilder, insert a mutex component, giva a value != 0, and the note appears :-) ) that CPUIDs are assigned from 0 upwards following the CPU order in the SOPCBuilder list.  bye  Paolo

[Altera_Forum]

Hello, 

 I have had similar problems running the multiprocessor tutorial - I got no text output in the IDE Console window, but the code appeared to be running as I could use debug mode and single step etc.  I am also using Quartus II 5.1 with Nios II 5.1, am using the Cyclone II Edition dev kit board and built a hardware design based on the Standard project.  I wondered if there was a cpuid problem, as that would cause problems for the &#39;generic&#39; source code, which relies on the cpuid to tailor the program flow for specific CPUs (and more specifically, to perform the JTAG UART comms [only] on cpu1, as that is where the JTAG UART is assumed - by the supplied hello_world_multi.c source file - to be attached)     --- Quote Start ---  originally posted by paolo.gai@Jan 7 2006, 10:16 AM ...about the cpu 1 id... when you debug, you can find the cpu id in the register window of the debugger... what are the values for the three cpus?  <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12032)  --- quote end ---    --- Quote End ---     So I ran the system in Debug mode, where it breakpoints at main() - then single-stepped each CPU in turn until the CPUID control register is read (via the macro call NIOS2_READ_CPUID(id) )  The following cpuid allocations were observed:  SOPC CPU Name -> cpuid register -> id variable (after the "id += 1;" ) cpu1 -> 2 -> 3 cpu2 -> 0 -> 1 cpu3 -> 1 -> 2  These values tie up with the NIOS2_CPU_ID_VALUE# defines that can be seen in the three &#39;system.h&#39; header files, and the values in the system definition (.ptf) file.     --- Quote Start ---  originally posted by baycool@Jan 10 2006, 02:57 AM however, in the tutorial my cpu 1 is assigned a cpuid = 0x2. i looked back over the tutorial, and this value is assigned by system. i am not sure how system makes this assignement but it is not based, i believe on the names of the cpu in sopc. this is where the potential for the bug lies.if you follow the tutorial you connect your jtag uart to cpu1 assuming that the system will assign cpu1= 0x0. if the system assigns another value to this register then you have a problem  <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12079)  --- quote end ---    --- Quote End ---    So, for me, cpu1 was assigned cpuid = 0x2, as for baycool...   Therefore, it is the s/w executing on cpu2 that will run the printf(...) code ; but cpu2 is not connected to the JTAG UART, so no output!  baycool&#39;s solution, to connect the JTAG UART to cpu2 instead of cpu1 is one workaround.  I tried modifying the software instead, so that it checked for an id variable value of 3, instead of 1 :      //if(id == 1)   // fudged code:  if(id == 3)  and this worked for me...    --- Quote Start ---  originally posted by paolo.gai@Jan 10 2006, 08:44 AM the best thing imho would have been either to be able to assign the cpuid values directly, or to have a combo box in the mutex component.  in any case, the problems seems to be solved in nios ii 5.1 where it is clearly stated in a subnote of the mutex component (open sopcbuilder, insert a mutex component, giva a value != 0, and the note appears :-) ) that cpuids are assigned from 0 upwards following the cpu order in the sopcbuilder list.  <div align='right'><{post_snapback}> (index.php?act=findpost&pid=12091)  --- quote end ---    --- Quote End ---    It would definitely be good if the CPUID values could be assigned in SOPC Builder! Failing that, the CPUID value should be visible in SOPC Builder, rather than having to dig around in header files etc. I see the subnote that paolo refers to, but it seems to be that CPUIDs are *not* being assigned "from 0 upwards following the CPU order in the SOPCBuilder list" (at least for me and baycool!). I have cpu1, cpu2 and cpu3, in that order, top to bottom, in SOPC Builder. I am using SOPC Builder 5.1 from the Quartus II 5.1 installation.  Anybody have any more insight into why SOPCBuilder is assigning CPUIDs this way?  Regards Mike

[Altera_Forum]

Hello,supertramp. 

I meet the prolbem of CPUID.But I modify "if(id == 1) " with "if(id == 3)" in every hello_world_multi.c,but there still aren&#39;t message showed in console window. if I download programmer of CPU1,CPU1 can printf message.But if I download programmer of CPU1,CPU2 and CPU3,there aren&#39;t message showed in console window. I am running the Standard project for the Altera Cyclone II EP2C35 dev kit.I am using Quartus 5.1 +SP2with Nios II 5.1. Anyone else meet the same problem with mine?if you solve,please tell me how to handle with it.

[Altera_Forum]

--- Quote Start ---  originally posted by hhh_gjf@Mar 28 2006, 03:08 PM hello,supertramp. i meet the prolbem of cpuid.but i modify "if(id == 1) " with "if(id == 3)" in every hello_world_multi.c,but  there still aren&#39;t  message showed in console window. if i download programmer of cpu1,cpu1 can printf message.but if i download programmer of cpu1,cpu2 and cpu3,there  aren&#39;t  message showed in console window. i am running the standard project for the altera cyclone ii ep2c35 dev kit.i am using quartus 5.1 +sp2with nios ii 5.1. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13863)  --- quote end ---    --- Quote End ---    Quite strange... the JTAG UART does have no relationship with multicore systems... did you tried in loading a hello world applicatio simultaneously in each core? in that case, the cores having the JTAG should print. Also check the reset addresses of your CPUs...     --- Quote Start ---  originally posted by hhh_gjf@Mar 28 2006, 03:08 PM anyone else meet the same problem with mine?if you solve,please tell me how to handle with it. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13863)  --- quote end ---    --- Quote End ---    The only workaround I see is not to use code that depends on the CPUID value...  Paolo

[Altera_Forum]

hello ,paolo.gai, Thank you for your reply. 

I use altera EP2C35 board ,quartus5.1+sp2 ,NiosIDE 5.1+sp1. I use "standard" example and do as tuturial. when I debug "NIOS2_READ_CPUID(id) ,id + =1;",I found the id of CPU1 which connected with JTAG_UART is 3; so I modify anywhere the "if(id == 1)" with "if(id == 3)". when I download "Collection" in which I check CPU1 ,CPU2 and CPU3 &#39;s programmer ,there is no message. I can&#39;t understand why? But I download "Collection" in which I check CPU1 programmer Only. It can Work and printf message. I think whether CPU1 don&#39;t work,I want to find answer.  So,I creat a new multipeocessor system, Only CPU1 and CPU2; CPU1 control LCD and CPU2 control LED. CPU1 and CPU2 are separated and don&#39;t share memory(DDR_sdram are shared but share difference area as tuturial.).I meet the same question, when I download "Collection" in which I check CPU1 and CPU2 &#39;s programmer , Only LED can work ,LCD can&#39;t work; but when I download "Collection" in which I check CPU1&#39;s programmer only, LCD can work; I enter into Debug mode,I found CPU1 and CPU2 can work when I debug! How Strange!  so I think whether Quaruts 5.1+sp2 has bug?   Regards gjf

[Altera_Forum]

Yes... the behavior is quite strange. 

 - for sure I can confirm also in other demos I did that CPUID are not assigned in the order they appear in the SOPCBuilder Tab.  - the behavior you are having is quite strange... The only times a CPU stopped workning when downloading the other one was when by downloading the second I was also reprogramming the FPGA... or when the 2 CPUs were sharing the data space, which is not your case...  - whan you say "no message appears", what do you mean? does the Nios II terminal starts correctly?  Paolo

[Altera_Forum]

Thank you ,paolo.gai."no message appears", mean that in my Nios II terminal ,there is no print message as tuturial.

[Altera_Forum]

--- Quote Start ---  originally posted by hhh_gjf@Apr 3 2006, 05:11 AM thank you ,paolo.gai."no message appears", mean that in my nios ii terminal ,there is no print  message as tuturial. <div align='right'><{post_snapback}> (index.php?act=findpost&pid=13976)  --- quote end ---    --- Quote End ---    ...ok... so I guess the terminal started correctly.  Also check that the system library for each CPU has the right jtag uart set up, and also check all the debug configuration...  After that, I have no idea, because JTAG uarts have always been working for me...  Paolo