Vhdl question

[Altera_Forum]

I come on this pice of code: 

  SIGNAL clockticks200k: INTEGER RANGE 0 TO max200k;  What dose Range stand for?

[Altera_Forum]

--- Quote Start ---  I come on this pice of code:   SIGNAL clockticks200k: INTEGER RANGE 0 TO max200k;  What dose Range stand for?  --- Quote End ---    The word range is used here to constrain the signal clockticks200k to the range 0<=clockticks200k<=max200k. If the value that clockticks200k ever evaluates to something outside of this range, a simulator will assert an error telling you so.  If the signal were declared: SIGNAL clockticks200k: INTEGER; no such checks would be performed.  Range constraining is a good practice if you know the bounds of the values. It provides a free assertion for you in your VHDL code without having to actually code an assertion.

[Altera_Forum]

Thank you.

[Altera_Forum]

You're welcome. 

 I should have also mentioned that a range constraint also guides the synthesis tool. The synthesis tool should only use as much resources as are necessary to represent the outer bounds of the integer range of the declared signal.