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In Nios2 Processor Handbook I'd noticed tha there is only one word per data chache line.
Why had altera designed that ? In my mind the data cache would slow data traffic severity, because the cpu data master isn't latency-aware. It's that? I'm really mixed ! Maybe we can design a own's data cache port? Had Anybody do it?Link Copied
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Some helpful changes along these lines are coming in the next Nios II release. Sorry I cannot be more specific until the product is released (in the coming weeks).
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Thank you!
I'd liked to listen to this message http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif regards!
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