Why is Nios2 data chache line so short?

[Altera_Forum]

In Nios2 Processor Handbook I'd noticed tha there is only one word per data chache line. 

Why had altera designed that ? In my mind the data cache would slow data traffic severity, because the cpu data master isn't latency-aware. It's that? I'm really mixed !   Maybe we can design a own's data cache port? Had Anybody do it?

[Altera_Forum]

Some helpful changes along these lines are coming in the next Nios II release. Sorry I cannot be more specific until the product is released (in the coming weeks).

[Altera_Forum]

Thank you! 

I&#39;d liked to listen to this message http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif   regards!