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I am new in altera platform. I was reading the DMA functionalities. I read data sheet available for SG DMA and nirmal DMA controller, but I could not find few basic specification of DMA like their throughput and Clock-wise description of each signal. IS there any other datasheet available for those DMA?
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Chapters 25 and 26 of this document https://www.altera.com/en_us/pdfs/literature/ug/ug_embedded_ip.pdf describe SG and regular DMA core provided by Altera.
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Thank you for giving the document, but still I could not find and diagram for clock wise description of each signal of DMA
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Those signals are standard Avalon-MM bus. Look at the section "The Master Read and Write Ports" on page 26-3. It points to the Avalon bus interface specification.
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