issue with program executing from SDRAM with NiosII/f core(cache4KB)

[Altera_Forum]

Hi, 

 I am using a NiosII fast core with cache size 4KB. i have an SDRAM controller. The system frequency is 50MHz. SDRAm freq=50MHz. The Issue is when the program, data, R/W memory is made as SDRAM and executed, then the program downloading is happening fine on SDRAM, but the program is not getting executed from the SDRAM. if the cache is removed(i.e NiosII/e is chosen) and tested, then the same program is able to execute from SDRAM. Can anyone suggest me?   Regards, Shubha

[Altera_Forum]

it is probably an sdram timing issue. when downloading and verifying the read / write speeds are very slow and never back to back. Without a cache, nios will also never have read or write transactions occur consecutively. 

 With the cache enabled, burst transactions occur, which can cause sdram timing issues to be exhibited. it is best to test the sdram interface with a dm type transaction.  --dalon

[Altera_Forum]

your pll generates 2 clocks 

C0 50MHz SDRamClk +90degree phase shift C1 50MHz Sysclock  first of all i would change the phase shift from +90 to -45, thats a value we use from 48 up to 64MHz SDRam and the phase calculations acc. to the app.note A??? gives results in that area. but you should check the timing relation between your sdram clock and nRAS. the clock edge needs to be in the middle. not shure if it is the pos edge. see sdram chip data sheet  with quartus 9.1 i can't open the sopc section of your design. so i can't give you more informations here. sorry. i can't find the *.sopcinfo file.  next step ...  limit the current strength for the sdram interface with the assignment editor. depending on your target, i would start with 12mA. this helps preventing over and undershots on those signals.

[Altera_Forum]

To properly test memory I would also slam it with DMA accesses with known memory test patterns like PRBS, 0x5A, etc... First get a CPU test running and then move on to the DMA test.

[Altera_Forum]

Hi all, 

 thanks for the suggestions. i have changed the timing parameters of the SDRAM as per the datasheet and as specified in the controller. the clock phase is given as 2.18 ns (around 39.24 degree). but still i have the samw issue. i have only SDRAM as memory and no other memory for text and data.   Shubha

[Altera_Forum]

Hi All, 

 Thank you for your suggestions. i was able to resolve the issue with the SDRAM by changing the SDRAM clk phase lag w.r.t to the controller clock by trial and error method. the clock now given is -45 degree w.r.t controller clock.  Thanks Again...  Regards, Shubha

[Altera_Forum]

good that you found a solution. 

but -45 is nealy the same value but the opposit direction than your 39 degree pahse shift. are you shure your calculation gave you +39 degree ?  one thing you can check and should check to be shure the phase shift is with a correct range, cool down the design. this will show if the hold timing works, as cooler chips are getting faster ...