max10 remote system update nios with uart

[aiedb]

hii 

i am trying to follow the application note to build a system to do a remote update of max10 over uart with nios 2 

i built the qsys system with the on chip flash in order to store a factory and application rpd files

i attached the image of the on chip flash configuration i configured it as a dual compressed image in order for the cfm sections to be available to store the files 

in the internal configuration under assignments-> device ->devices and pins -> configuration

  i choose dual compress image the same as on chip flash configuration 

also here i attached the image of my configuration

but when i compile the design i get this error

Current Internal Configuration mode does not support memory initialization or ROM. 

Select Internal Configuration mode with ERAM

that does not make sense to me cause i am using dual compressed image  , i be glad for help or to see if i made a mistake in my configurations  

[sstrell]

What's your target device?  10M02 does not support this (only has CFM0).

[FvM]

Hi,
I see that the target device is 10M50DA, thus it is supporting remote system upgrade with dual compressed image. But due to inherent limitation of MAX10 series, you can't have dual image and internal ROM at the same time. Respectively NIOS processor can be only booted from external SPI flash, see AN741.

Regards
Frank

[sstrell]

Ah, missed that on the error screenshot.

[aiedb]

hii frank thanks for your reply i saw in example design that is published in altera store called max10_rsu that  they used both on chip flash and ram memory  for the nios 2

i attached the picture of the nios 2 configurations and you can see that the picture that the nios 2  reset vector memory  is  configured to be generic quad spi controller and the exception vector memory is on chip memory 

and if i understand you correctly i only need qspi as a memory for nios 2 ? so what do i need to do ? i built my system according to the altera example 

1-do i need to set the exception vector also to generic quad spi controller also? and remove the on chip memory from my system 

i be glad for help ?

[Sparrow_Altera]

Hello

Can you check your design settings in Quartus with the example design settings, the link below provides the file for the example that you are trying to follow 

Intel® MAX® 10 FPGA – Intel MAX 10 FPGA Remote System Upgrade (RSU) over UART for the Nios® II Processor Design Example

Thanks

[aiedb]

hii when i compile this project i get errors due to licince issues how can i solve it ?

[Sparrow_Altera]

Hello

Let me check and get back to you. Thanks.

[Sparrow_Altera]

Hello

Nios II is EOL, Altera stop selling Nios II/f license.

New users need to migrate to Nios V and apply the Nios V license.

Regarding the example design, couple of points below that can help you.

To simplify the design, it can be divided into three function blocks:

• RSU block (Dual Configuration IP to handle RSU)
• UART block (Communication thru UART)
• Booting block (Nios to boot from QSPI)

RSU block (Dual Configuration IP to handle RSU)

UART block (Communication thru UART, such as printf & scanf)

Booting block (Nios booting from QSPI)

Below User Guides will help you to understand more about these function blocks.

RSU block (Dual Configuration IP to handle RSU)

• MAX® 10 FPGA Configuration User Guide (How does Dual Configuration IP handle Max 10 RSU?)
• MAX® 10 User Flash Memory User Guide (Dual Configuration IP switches the target CFM only, you will need On-Chip Flash IP to change the FPGA Image in CFM)

UART block (Communication thru UART)

• UART Core (Altera HAL driver to send/receive UART data in Software Programming Model subchapter)

Booting block (Nios booting from QSPI)

• Nios® II Processor Booting from QSPI Flash (QSPI Controller + OCRAM is a must to boot Nios II from QSPI)
• Nios® V Processor Booting from General Purpose QSPI Flash (QSPI Controller + OCRAM is a must to boot Nios V from QSPI)

And finally connecting the 3 logic blocks to get the whole design,

Thanks

[aiedb]

hii thanks a lot for reply that helped me alot now i understand what is the problem 

[Sparrow_Altera]

That's great, glad that helped.

Thanks

[aiedb]

hii

do you have a design guide that explains how to do RSU without the need of a nios 2 processor

lets say i want to write my own vhdl code to perform the rsu , from what i understand

1- i need to be able to read and write the cfm sections in order to write the my image  into cfm0 and cfm1/2 in dual compressed mode

2- trigger the fpga in order to read the new image from cfm1/2 and configure the fpga logic by hardware or software 

i would like to know if there an application note that explains how to do RSU manually without the help of nios 

3- another question if i configure the nios v processor to boot from qspi  does it take up from the logic elements ?

[SueC_Altera]

Hi Aiedb,

It is helpful to start a new thread for new questions.

I hope you have read the Max10 configuration user guide - it has a detailed RSU section.

Sue

[Sparrow_Altera]

Hello

Please open a new thread for this item as this is a new topic.

Thanks

[BoonBengT_Altera]

Hi @aiedb,

As previous clarificcation has been attended, with no further clarification on this thread, it will be transitioned to community support for further help on doubts in this thread. 

Please login to ‘ https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you for the questions and as always pleasure having you here.

Best Wishes

BB