running program in SRAM doesn't work

[Altera_Forum]

Hi all, 

 I am running my C program in NiosII and I need to print out the result on the console. There are a 512KB SRAM and an 8MB SDRAM on the board.  The program works fine with the SDRAM.  However when I changed all the program sections' specification to SRAM in the BSP Editor (in the Nios II SBT), the program can be downloaded to the board but it shows nothing on the NiosII Console.  My program is 106KB so should be possible to run in SRAM.  Anybody who can tell me possible reasons why it happens?

[Altera_Forum]

Did you remember to change the nios cpu's reset/exception vector? 

These may need to correct even when loading from jtag.

[Altera_Forum]

hi dsl 

Thank you for your reply. I changed the reset/exception vector to the SRAM but it still doesn't work...

[Altera_Forum]

Hi srhikari, 

 Did you get this working?  I have exactly the same problem trying to run the software on SRAM. I even tried running it on the Cyclone III NEEK dev kit with the same results. It runs fine with SW running in SDRAM, but no Nios II Console output when using SSRAM.  Yet another glitch in Qsys/Nios II. Please let us know if you find a solution, I will do the same.

[Altera_Forum]

sorry can't help you :( 

it still doesn't work so i skipped it and run in SDRAM

[Altera_Forum]

did somebody make to run a program in sram?

[Altera_Forum]

--- Quote Start ---  did somebody make to run a program in sram?  --- Quote End ---    Yes, but there are lots of things to consider - proper pin connectivity, control signal polarity, Qsys configuration, Generic Tristate Controller configuration, timing closure, etc.  This is a custom board, I presume?  Can you provide a screen shot of your Qsys design?

[Altera_Forum]

Hi, do you have flash in ur qsys system? If yes, I suppose you are gonna have 2 generic tristate controllers, tristate bridge and a tristate pin sharer connecting together. In your top level design, pls check its connection. For 16 bit sram, u should ignore the first bit and so on. I encourage you to have a look on qsys handbook, Tristate chapter. Hope it helps.

[Altera_Forum]

thank fheineman and caridee, 

 here you have a screem shot but i m using SOPC builder instead of Qsys (and Quartus II 11.0sp1 Web Edition (32-Bit)).can thAT generate any problem?  My board is cyclone iv DE2-115.    my project run from sdram but when i change linker region(BSP editor), reset vector and exception vector(SOPC) from sdram to sram, the file .elf cant be downloaded:  "Hardware configuration' has encountered a problem. Downloading ELF Process failed"

[Altera_Forum]

--- Quote Start ---  Hi, do you have flash in ur qsys system? If yes, I suppose you are gonna have 2 generic tristate controllers, tristate bridge and a tristate pin sharer connecting together. In your top level design, pls check its connection. For 16 bit sram, u should ignore the first bit and so on. I encourage you to have a look on qsys handbook, Tristate chapter. Hope it helps.  --- Quote End ---    PeFarina, It is a common practice to share address and data pins between SRAM and Flash memory to reduce the number of pins required in your FPGA design. If this is your case, you need to add a pin-sharer module in SOPC Builder. I'm more familiar with Qsys, but I imagine the configuration is similar. I attached a screen shot of my Qsys design to show how the pin sharer connects the SRAM and Flash. If you have separate address and data pins for your SRAM, then you don't need the pin sharer.

[Altera_Forum]

thank but i have separate address and data pins for my SRAM. i dont know what is wrong.

[Altera_Forum]

--- Quote Start ---  thank but i have separate address and data pins for my SRAM. i dont know what is wrong.  --- Quote End ---    How did you create your TERRASIC_SRAM component? Your connections in SOPC Builder look fine, so the problem should either be in the component configuration or the connections between the Altera FPGA and the SRAM.  Have you tried using System Console to check your SRAM as I described in a previous thread?

[Altera_Forum]

--- Quote Start ---  PeFarina, It is a common practice to share address and data pins between SRAM and Flash memory to reduce the number of pins required in your FPGA design. If this is your case, you need to add a pin-sharer module in SOPC Builder. I'm more familiar with Qsys, but I imagine the configuration is similar. I attached a screen shot of my Qsys design to show how the pin sharer connects the SRAM and Flash. If you have separate address and data pins for your SRAM, then you don't need the pin sharer.  --- Quote End ---    thanks,  i have separate address and data pins for my SRAM, i´ve checked on pin planner.   if i do a memory test as you have explained me( Tcl Console) does it mean that the sram component(terasic_sram) is working? or the access to memory is done by other way.  how can i see the value of vector reset?because i can move its address but i don know if when i change the files(.bss .heap .rodata .rwdata .stack .text) to sram the reset vector changes too.   if you want more info about my project i will send you.  i've attached the eclipse console

[Altera_Forum]

--- Quote Start ---     if i do a memory test as you have explained me( Tcl Console) does it mean that the sram component(terasic_sram) is working? or the access to memory is done by other way.  --- Quote End ---    Yes, if you test the memory with System Console following the procedure I gave you, it will tell you if a small portion of the SRAM is working or not. You can expand the amount of data written and read, or change the write and read addresses accordingly to test different segments of the SRAM. It is a good sanity check to se if the SRAM is functional, and an easy way to troubleshoot if not.    --- Quote Start ---   how can i see the value of vector reset?   --- Quote End ---    To set (and view) the Reset and Exception vectors, you must open the Nios II (cpu) component in your SOPC design and scroll down to the vector options. There you will have a drop-down list of possible locations for each vector. Choose sram from the list, then re-generate SOPC, re-compile your Quartus II design, and re-program your FPGA.     --- Quote Start ---   because i can move its address but i don know if when i change the files(.bss .heap .rodata .rwdata .stack .text) to sram the reset vector changes too.   --- Quote End ---    I presume by this that you are referring to the Linker Script tab in the BSP editor of the Eclipse SBT. After setting the vectors to sram as above, you should not have to change anything in the Linker Script. The .bss .heap .rodata .rwdata .stack .text regions (these are not files, but areas in memory assigned to the various code segments) as well as the Reset and Exception vectors should already be assigned to sram.

[Altera_Forum]

thanks again, 

 i found a weird behavior, when i test the sram it happens(attached screem shot:memory), some positions are wrong. why? isnt the physical device working? or isnt the sram component(TERRASIC_SRAM) working?  other thing is that i change the reset and exception vector in my SOPC design but when i open the BSP editor and i open the linker script just the reset and exception vector are in the sram(linker_script) so i have change manually it

[Altera_Forum]

--- Quote Start ---    i found a weird behavior, when i test the sram it happens(attached screem shot:memory), some positions are wrong. why? isnt the physical device working? or isnt the sram component(TERRASIC_SRAM) working?   --- Quote End ---    Okay, you definitely have a problem with the sram. Based on the information so far, it could be bad solder joints on the board, a timing issue, or both. The first thing I would do is issue several read commands in the System Console after the write command to see if the results change or stay the same. I'm not sure exactly what this would tell you, but it may help establish a pattern to the behavior. I don't really see one yet. Perhaps someone else does...    --- Quote Start ---   other thing is that i change the reset and exception vector in my SOPC design but when i open the BSP editor and i open the linker script just the reset and exception vector are in the sram(linker_script) so i have change manually it  --- Quote End ---    This may be left over from what you had set up previously. Best to get the sram working with System Console first, then come back to this.

[Altera_Forum]

i have change the system frecuency(100mhz to 50mhz because the SRAM high-speed access time is 10ns)then i dont have error in the TcL test. MOreover i change the jtag_uart IRQ(0 to 16) and after all of this the downloading and verifying is completed but the programs doesnt seem work, there arent messages on the nios console. 

 why is the nios program downloaded and verified changing IRQ?  what happens with the console?  thanks

[Altera_Forum]

--- Quote Start ---   i have change the system frecuency(100mhz to 50mhz because the SRAM high-speed access time is 10ns)then i dont have error in the TcL test. MOreover i change the jtag_uart IRQ(0 to 16) and after all of this the downloading and verifying is completed but the programs doesnt seem work, there arent messages on the nios console.  why is the nios program downloaded and verified changing IRQ?  what happens with the console?    --- Quote End ---    Any time I've run into this situation where the ELF file downloads and verifies properly, but there is no output to the Nios II Console, it has been due to a timing issue with the Quartus design.  If you haven't already, you should run TimeQuest from within Quartus II and constrain the clocks. Create an SDC file from this, then re-compile your Quartus project. Be sure to include the newly created SDC file in your project before re-compiling. Don't forget to program your FPGA with the new SOF before running the software.

[Altera_Forum]

I'm trying to do the same as the OP with a DE2-115 and run all the nios on the SRAM. 

It must be the terasic SRAM core, there must be something missing with that.   The problem i get is the elf fails to download. Very annoying, i've tried a number of methods with no luck. For note the DE2-115 SRAM shares no pins with anything else.

[Altera_Forum]

If you use Qsys it should be possible to parametize the generic tristate controller with the SRAM timing values to create your own controller for that memory.

[Altera_Forum]

I feel like a *****, but i tried to make my own tri-state version as suggested by BadOmen; but this failed. I require more help and would be greatly appreciative. 

It failed the same as before with the .elf failing verification upon download. Likely because i have no idea how to set up the Tri-state controller, i did alot of googling and read some doco and made an attempt anyway.   I have attached a zip file with screenshots of my attempt. In summary but my problems were: 

1. signals?:Couldn't match my SRAM's signals to those avaliable in the Tristate controller. My SRAM has no read enable, it also has two other signals, upper and lower?  I took a guess that these two mystery signals could be bridged to WE since they appear optional and a timing diagram where they were used they matched WE. 
2. parameters had me stumped. I used the preset on the right for the IDT SRAM as a starter. Two worse ones was that driver one since it made no sense what the preset put there. Plus i put the bytes value there, but am i meant to take some off? As in 2MB seems too round? 
3. timings: I couldn't match the timings. In many cases i made an educated guess or put a worse case value. 

what i tried summary 

1. Made simple Qsys design of nios. Onchip ram contains Nios vectors. 
2. Made tri-state control and connected to a tri-state bridge. note i doubt the control is correct. 
3. Made top level and bridge the 3 signal WE,UB, LB. 
4. Made simple "Hello World Nios" and pointed its memory to the SRAM controller. 

attached 

1. Data sheet. Note that its the 8ns model. 
2. QSys image. 
3. Tri-state control set up images.