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Hello,
I am currently working on my own slave component. I've written and tested the 32-bit input version and it worked well. Now I have 64-bit input version. I know that nios cpu handles 32-bit only but I have to transfer 64-bit vector somehow... I read a lot about memory maped slave intefaces, esspecially mm bus specification and I found out that I have to use the byteenable signal. I'd like to send 64-bit in two parts 0-31 and 63-32 I know it corresponds to offset 0x0 and 0x04. What should be the value of byteenable signal in such operation? Altera gives only a table of Byte Enable Usage for 32-bit Slave... Thanks in advance for any help!Link Copied
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The valid cases are all those where the access has the same alignment as it's width.
For a 64 bit slave, the bytenable signal is 8 bits wide and the following valid cases. 64 bit accesses (0x0 to 0x7): 1111_1111 32 bit accesses: 0000_1111 (0x0 to 0x3); 1111_0000 (0x4 to 0x7) 16 bit accesses 0000_0011; 0000_1100; 0011_0000; 1100_0000 8 bit accesses 0000_0001; ...; 1000_0000- Mark as New
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thanks for answer.
You're right I'am a little bit confused about this solution. byteenable should be 8bytes, I understand. but how all operation of data transfer should look like? To send 64-bit vector from nios to slave input do i have to do it like this: set the byteenable to 0000_1111 send 64-bit data (the master will send first 32-bit) then set the byteenable to 1111_0000 send 64-bit data (the master will send last 32-bit) am i right or did i missunderstood the whole process? Maybe there is a easier solution for such transfer?- Mark as New
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Jason,
You don't set byteenable -- it's done for you automatically by the master/fabric. Your slave just has to handle it properly. A 64 bit transfer will look much like you described it. First, your NIOS program issues a 32 bit write to SLAVE_ADDR+0x0. Your slave will see a write to 0x0 with byteenable set to 0000_1111. Next, your NIOS program issues another 32 bit write to SLAVE_ADDR+0x4. Your slave will see a write to 0x0 with byteenable set to 1111_0000.- Mark as New
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Thank You very much, to be sure would the following code act correctly?
avs_we_writedata: in std_logic_vector(0 downto 63); --the input
(...)
--then i declare two internal signals
signal register_1: std_logic_vector(0 downto 31);
signal register_2: std_logic_vector(0 downto 31);
--and then in process
if avs_we_byteenable = "00001111" then
register_1 <= avs_we_writedata(31 downto 0);
register_2 <=register_2;
elsif avs_we_byteenable = "11110000" then
register_1 <=register_1;
register_2 <= avs_we_writedata(63 downto 32);
else
register_1 <= register_1;
register_2 <= register_2;
end if;
and in software should i use IOWR(COMPONENT_IN_BASE, 0, vector_64bit);
or IOWR(COMPONENT_IN_BASE, 0x0, vector_1_32bit);
IOWR(COMPONENT_IN_BASE, 0x4, vector_2_32bit);
? I am a little bit confused Thanks in advance
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Your VHDL looks ok, but I'd advise you to also support the 16 and 8 bit cases...
In software, it shall be the second form.- Mark as New
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--- Quote Start --- Your VHDL looks ok, but I'd advise you to also support the 16 and 8 bit cases... In software, it shall be the second form. --- Quote End --- Hmm well so I have to split my data into two 32bit vectors? Are you sure? in this case shouldn't be there 32bit input?
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At the software level, yes.
NIOS II is a 32 bit CPU, it has no instructions to read or write 64 bits at once. And it's only available with a 32 bit interface, anyway. What do you mean by "shouldn't be there 32bit input" ?- Mark as New
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--- Quote Start --- At the software level, yes. NIOS II is a 32 bit CPU, it has no instructions to read or write 64 bits at once. And it's only available with a 32 bit interface, anyway. --- Quote End --- Ok I see the point, but I have a lot of data in hex 64-bit format, so now I have to convert it to binary and split into 32bit vectors and then go to hex, am I right? Is it possible to send binary vector using IOWR? Thanks
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IOWR writes binary data. It takes a alt_u32 parameter and writes the exact same bits to the specified address.

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