10M25DAF484C8G clock input

[joe_su]

Hi 

we have serveral CML clocks output from ethernet PHY which is connected to 10M25DAF484C8G pin P3/R3, V9/V10, how to design the convertion circuit as CML(PHY) to LVDS(max10) ?

and if we want to output these diff-clock signal, what type it should be ? what type diff-clock does 10M25DA support output ?

//Joe

[ShengN_Intel]

Hi,

If voltage of CML and LVDS are not the same, can use below:

If low speed, you can use voltage divider.

If high speed, you need to use level shifter.

If voltage of CML and LVDS are same, not need to use.

And also the external termination circuit:

https://www.intel.com/content/www/us/en/docs/programmable/683760/22-1/lvds-1-8-v-lvds-mini-lvds-and-rsds-receiver.html

The Max 10 lvds IO Standard can refer this :

https://www.intel.com/content/www/us/en/docs/programmable/683760/24-1/lvds-serdes-i-o-standards-support.html

Thanks,

Regards,

Sheng

[ShengN_Intel]

Hi,

This is example of level shifter:

https://www.analog.com/en/products/max9376.html

Guarantee for high speed.

Thanks,

Regards,

Sheng

[FvM]

Hi,

you usually don't need a level shifter for clock signal. For clock belo 500 MHz, MAX 10 LVDS input has 0.05 - 1.8 V common mode range which most likely fits the CML signal. If not, you can use AC coupling with bias to 1.25 V on the FPGA side. 

Similarly, LVDS output driver will most likely fit level requirements of CML input on other device.

Regards
Frank

[ShengN_Intel]

Hi,

AC coupling circuit can refer here:

https://www.intel.com/content/www/us/en/docs/programmable/683760/22-1/lvpecl-external-termination.html

Thanks,

Regards,

Sheng