Hi!
Thinking about how to implement a fully reconfigurable design where there my Ethernet PHY supporting 10M/100M/1000M/10G speeds is connected to my ArriaV GX via XAUI. In order to be able to operate at other speeds than 10G the PHY reconfigures its XAUI to SGMII (only one lane in use @ 1.25Gbps). How should I accommodate for that on my FPGA? Is there a way to have transceivers reconfigured between 4-lane XAUI @ 3.125G and 1-lane SGMII @ 1.25G and vice versa?
