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sdram DE0-nano - PLL phase shift

Honored Contributor II



There is something I don't fully understand in the following tutorial: 


On page 11, Chapter 7, it is said: 

"... The clock skew depends on physical characteristics of the DE0-Nano board. For proper operation of the SDRAM chip, it is necessary that its clock signal, DRAM_CLK, leads the Nios II system clock, CLOCK_50, by 3 nanoseconds...." 


My question is: Are those 3 nanoseconds a constant whatever the frequency is? 

In my project, I would like to run the SDRAM and its controller at 143MHz. Should I keep the delay of 3 ns or keep a phase shift of 54 degrees? 


I would be tempted to tell that as it is linked to a board property, a delay doesn't depend on frequency. So I should keep the 3 ns delay which correspond to a phase shift of 154.3 degrees. 


What do you think? 


Thank you for your help 



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