A question about generating a PCIe R-tile design example

[xingyunzhidi]

I would like to generate a PCIe R-tile design example for MCIO pins. However, I am unable to select the interface type in the design example generation interface. Would it be acceptable to modify the PCIe-related pins in the constraint file to MCIO pins after generating the design example?

[Wincent_Altera]

Hi,

For PCIe gen 5 R-tile, you can generate from our Quartus IP Catalog.

If you need detail about the system level implementation , you may refer to

https://community.intel.com/t5/FPGA-Intellectual-Property/How-to-run-PCIe-Gen-5-Design-Example-using-Altera-FPGA-device/td-p/1640988

But , those are not supporting MCIO, user is advise to customize the pin in order to support MCIO implementation.

Detail about the PIN, you may refer to

1. Board schematic DK-DEV-AGI027R1BES
2. Connector detail A.4. MCIO Connector

Regards,

Wincent_Altera

[Wincent_Altera]

Hi,

I wish to follow up with you about this case. Do you have any further questions on this matter ?

Regards,

Wincent_Altera

[Wincent_Altera]

Hi,

As we do not receive any response from you on previous question/reply/answer that we provided. Please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of desire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.

Regards,

Wincent_Altera

[Wincent_Altera]

Hi,

As we do not receive any response from you on previous question/reply/answer that we provided. Please login to “https://supporttickets.intel.com/s/?language=en_US’, view details of desire request, and post a feed/response within net 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on follow-up questions.

Regards,

Wincent_Altera