A10 IOPLL not locked

[Rleduc]

Hello dear community,

I am currently working on A10 (Terasic HAN Pilot Plateform - 10AS066K3F40E2SG) , and using external clock as reference clock for an IOPLL to generate 2 outputs :  1 which is same frequency, and 1 which is twice lower.

For instance, my 1st config is CLKref = 125 MHz ; CLK_out1 = 125 MHz ; CLK_out2 = 62.5 MHz. Everything works fine and PLL will lock with no problem.

Now when I double CLKref to 250 MHz and double outputs frequency, the IOPLL will lock but unlock for 1 clock period every 8 periods, which makes it unusable.

I checked on signaltap by sampling with higher clock rate, and I can properly see the input clock at 250 MHz with steady period. I ensured aswell that my clock signal has good integrity on scope, and I assigned the input in pin planner to dedicated REFCLK differential transceiver LVDS, terminated with 100 ohms. 

Once again it works at 125MHz, but not 250MHz.

If you have any suggestion in what is causing this issue you're very welcome,

Roman 

[AqidAyman_Intel]

Hi Roman,

1) Are you reconfiguring the PLL, or using a different FPGA programming file when switching between these two reference clock frequencies? For example, an I/O PLL which is configured to accept a 125MHz input clock is expected to lock to that frequency but if the I/O PLL is configured to accept a 125MHz clock, it may not be able to lock to 250MHz. Each PLL configuration is tuned for a specific input clock frequency, which has some range above and below that frequency. But a large difference could be outside of that range. Here is a KDB article which was wrote a very long time ago which suggests using clock switchover to see if the PLL can be legally configured to accept two different clock frequencies. Note this was written for the ALTPLL IP in older families, so it will be a little different for I/O PLLs in Arria 10, and I don’t think Quartus reports the lock range of the PLLs in the fitter report for newer families. https://www.intel.com/content/www/us/en/support/programmable/articles/000073701.html

2) You said this clock source is on a transceiver REFCLK pin, not a dedicated clock pin in the GPIO? If it’s a transceiver REFCLK, then it’s not the best source for an I/O PLL clock, it may be picking up additional jitter on a global network which is likely required to drive the I/O PLL from that remote source. Perhaps at 250MHz the clock source has higher jitter than at 125MHz, or the I/O PLL is more sensitive to jitter at that frequency.

[AqidAyman_Intel]

Hi,

Do you have any more concern on this issue?

[AqidAyman_Intel]

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