ACEX1k

[Altera_Forum]

Hello Guys 

I am using the ACEX 1k ALTERA with MAXPLUSII In my FPGA I have a 48Mhz clk, in some where I use the 48Mhz clk as input to a "CLKLOCK" block that make from this 48Mhz clk a 96Mhz clk, the problem is when i want to use this 96Mhz clk i most use it as a input to a clk flipflop. how can i use this 96Mhz ? or what i can do to use this clk not with a flipflop? or how can i crate this clk "maybe without using the CLKLOCK". What i need is to use this 96Mhz clk in my counter how can i do that. thx a lot

[Altera_Forum]

You want to use the 96MHz clock as logic? From what I remember of that family, once you're on a clock tree(which is what the clklock block feeds), there is no way to get off of it. You can go off chip and route back in, or multiply up to 192MHz(if possible) and create a divide by two register.  

All new families can get off the clock tree though, if that's an option.

[Altera_Forum]

Hey 

first thanks for ur help but : I do not think that i can use 196Mhz, this is not possible in ACEX 1K. what is a clk tree ? thanks Amirster

[Altera_Forum]

Clock tree is the pre-done, low skew routing tree that is done in the hardware to distrubute clocks throughout the device. In the Acex 1K family I think it only fed the clock ports of registers.  

 If you're clock rate is 96MHz, hence your data rate is 96MHz, why do you need a signal that transitions twice(one rising and one falling edge) per clock? Are you using negative edge registers, maybe doing a double-data rate application?