Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

ADC JESD204B over xcvr lanes

Altera_Forum
Honored Contributor II
‎05-06-2015 06:05 PM
1,285 Views

Hello, 

 

I have a development board which has SFP+ cages that are hooked up to the xcvr inputs on a Stratix V FPGA development board. I am wondering if I can receive and decode JESD204B signals over this connection. Can Altera's JESD204B ip target the xcvr inputs lanes? If not, can I still write my own and by using transceivers in some custom configuration? 

 

Thank you for the insights.
0 Kudos

Link Copied

2 Replies
Altera_Forum
Honored Contributor II
‎05-13-2015 12:32 AM
567 Views

Ideally there should not be an issue to connect the IP to the XCVR input lanes because the XCVR lanes should be independent from the IP core. The quick way to verify this would be to get the JESD IP and then try to place at the specific lane that you are targeting. Then run through Fitter compilation. Fitter will help to check against placement rules and restrictions. If the IP not allow, you can try the same method with your custom XCVR ie with Custom PHY or Native PHY.

0 Kudos
Copy link
Altera_Forum
Honored Contributor II
‎08-24-2015 08:13 PM
567 Views

Hi, did you get a solution to your problem? Also, can you run the JESD megafunction without using a NIOS processor?

0 Kudos
Copy link
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.