I'm investigating a Cyclone V design with 32 LVDS input channels running near 1Gbps each. The skew between channels is likely to be near, or even exceeding one UI, therefore it won't be possible to simply choose a sampling clock phase that hits all the input lines at an appropriate sampling point. Here are some target specs;
Cyclone V
ALTLVDS_RX Deserializer
32 channels
8 bit serialization
800Mbps per channel
Input data skew +/- 650 ps max
My questions;
1) If I know, or can measure the skew values between channels, can I add input delays to the fastest channels and make them "line up" more or less with the slower channels? Then I may have to shift my sampling clock to hit the appropriate sampling window.
2) Can I make Quartus do this for me automatically by setting appropriate constraints in the sdc file?
I suspect the answer is no to both, as programmable input delays can't be applied to LVDS inputs on the Cyclone V. Maybe there's another way to make this work?
