About the number of PLL outputs （CYCLONE5）

[testp]

About the number of output pins of the PLL

If you check CV-52004

Table 4-7: PLL Features in Cyclone V Devices

There is the following description in.

Dedicated external clock outputs
→ 2 single-ended and 1 differentia

Looking at the separate document (UG-01087),

The Altera PLL IP core can generate up to 18 clock output signals for the Stratix V and Arria V devices,
and nine clock output signals for the Cyclone V devices. The generated clock output signals clock the core
or the external blocks outside the core.

There is.

I think these two explain about the number of output pins of the PLL,
There is a difference in the number of outputs.

Why is there a difference?

When you check the IP settings in Qurtus Light Edition 18.1
9 The output looks correct.

2 single-ended and 1 differentia
Could you please tell me the reason why it is stated?

regards

[sstrell]

It's referring to what pins are dedicated clock output pins of the device.  You can have more clocks internal to the device that are not sent out the dedicated clock output pins.

[testp]

Thank you for your reply.
I saw the answer, but I didn't understand.

Device to be used: 5CEBA7F23C7N

I am thinking of using the above device.
From the contents of the answer
When the PLL is created with IP, 9 CLKs can be branched inside the FPGA,
FPLL_ [BL, BR, TL, TR] _CLKOUT0 (eg AH11) etc.
If you want to output to the CLK output dedicated pin
I understand that you can assign up to 2 singles.

One question comes up here.
The CYCLONE5 overview (see below) states that the maximum number of PLLs is 7.
I recognize this 7 as the number of pins that can be output to the outside.

Source: CV-51001
See also: Table 4. Maximum Resource Counts for Cyclone V E Devices
Item: PLL

I checked all the packages of CYCLONE5, but
Looking at the F31 type, the following eight pins are dedicated to CLK output.

FPLL_BL_CLKOUT0, FPLL_BL_CLKOUTp, FPLL_BL_FB (AH11)
FPLL_BL_CLKOUT1, FPLL_BL_CLKOUTn (AH12)
FPLL_BR_CLKOUT0, FPLL_BR_CLKOUTp, FPLL_BR_FB (Y30)
FPLL_BR_CLKOUT1, FPLL_BR_CLKOUTn (W30)
FPLL_TL_CLKOUT0, FPLL_TL_CLKOUTp, FPLL_TL_FB (F9)
FPLL_TL_CLKOUT1, FPLL_TL_CLKOUTn (E10)
FPLL_TR_CLKOUT0, FPLL_TR_CLKOUTp, FPLL_TR_FB (M29)
FPLL_TR_CLKOUT1, FPLL_TR_CLKOUTn (N30)

It looks like there is a difference from PLL7 mentioned in the overview,
What does PLL 7 in the overview mean?

[Ash_R_Intel · Accepted solution]

Hi,

The 'nine clock output signals for the Cyclone V devices' in Altera PLL IP core corresponds to

C output counters -> 9

in the Cyclone V handbook. These are the clocks generated from the PLL. 

The Dedicated external clock outputs represent the FPLL_<#>_CLKOUT pins on the device. You can connect any of the C output counters to external clock outputs. Refer 4.2.6. PLL External Clock I/O Pins of Device Handbook.

There are dedicated clock output pins associated with each corner fractional PLL.

So the main difference is that C counters are PLL outputs (internal to FPGA) whereas CLKOUT pins are device outputs (available external to the FPGA).

Regards