Facing Issue with Max10 CPLD, I can't define differential clock at my design.
I/O bank 6 is 1.8V, and I Used all Vref pins in the CPLD as single-ended I/O.
I tried to define the clock input as LVDS / Sub-LVDS , error :
Error (169029): Pin DIFF100_XTAL_OSC1_40MHZ is incompatible with I/O bank 6. Pin uses I/O standard Sub-LVDS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 1.8V.
Error (169032): I/O bank 6 contains input or bidirectional pins with I/O standards that make it impossible to choose a legal VCCIO value for the bank
I would appreciate help regarding the define differential clock in the bank of 1.8V ?
I have also Stratix10 FPGA and I succeeded to define LVDS inputs at 1.8V bank
May I know which version of Quartus are you using?
Try this workaround to solve Error 169029:
1. Remove the location assignment of pin_perst
2. Add a quartus.ini file in your project directory with: dft_skip_oct_vccn_check = on
Try this workaround to solve Error 169032
1. Assign 1.5V PCML I/O standard to Cyclone IV GX transceiver input pins.
Thanks AminT for the fast response.
the version is Quartus standard 19.1,
I added the quartus.ini file and define the clock pin as Sub-LVDS, the 2 error are gone ( 169029 & 169032 ).
what causes the error in Quartus ?
but still the question is technical, can I now connect to the Max10 differential clock (of 1.8V at bank of 1.8V
and there is no any Vref from the pins to the CPLD) and define it as LVDS ? Sub-LVDS ?
Do they require Vref ? and what with others differential I/O 's ?
The error is a known issue. You will need to refer to these two documents for your design I/O standard specification: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug-s10-gpio.p... and https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/s10_datasheet... .
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