Active serial configuration agilex 5

[Dany2]

Hi all

I have a question about the agilex 5 clocking scheme : 

In my design I need to use 3 IP

EMIF (lpddr4),

MIPI receiver, 

transceiver (HSSI)

The pcb is very compact, so I don't have a space to add many options.

Do I have to provide an external differential clock to each IP through the FPGA  pins, or I can feed one of the clk inputs with the single ended clock and than use an internal PLL and clock network to distribute a clk to each IP?

Thanks

Dany

[lixy]

Hi Dany2,

For Clock sharing, you may check GTS Transceiver PHY User Guide: Agilex™ 5 FPGAs and SoCs, 2.6.5. Shared Clocking Resources Between the GTS Transceiver Bank and....

https://www.intel.com/content/www/us/en/docs/programmable/817660/25-1/shared-clocking-resources-between-the.html

You may route the tx_clkout / rx_clkout signals etc from the GTS transceiver IP to core fabric. But as the frequency requirements of different functions you mentioned probably don't match with each other, this may not meet your need.

There's no direct way to feed the clock input from one pair of certain external differential clk pins to both Core fabric and Transceiver.

Best Regards,

Xiaoyan