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CHebl
Beginner
111 Views

After PreSICE calibration ATX PLL doesn't lock

Hi all,

I'm currently trying to reconfigure the ATX PLL of an Arria 10 device to a different data rate via HPS reconfiguration interface.
The IP is configured and fitted for 2400 Mbps operation (1200 MHz) with a free-running reference clock of 80 MHz with very good signal integrity (from LMK04828).
In a second step I generate the whole interface for 3200 Mbps (1600 MHz) and extract the reconfiguration register values from the QSys generated design (C-Header file).
After this I follow the reconfiguration guide and write all values of the Header file to the interface.
I read these values back before and after PreSICE calibration and found, that the engine overwrites the internal voltage regulator settings (Register 0x102 should be 0xB5 and is 0x15, Register 0x11C should be 0x00 and is 0x20).
Furthermore the PLL doesn't emit the pll_locked signal (checked with SignalTap). When reconfiguring to a rate of 4800 the pll_locked signal turns high, but PreCISE also changes values here.

I'm currently doing the following steps for reconfiguration:

1. Apply reset to ResetSequencer IP
2. Aquire arbitration (Write 2 to Address 0)
3. Wait for Address 0x280[2] == 0
4. Reconfigure ATX PLL
5. Write 1 to 0x100 (activates PreSICE calibration)
6. Release Arbitration (Write 1 to Address 0)
7. Wait for calibration done (0x280[1] == 0)
8. Release ResetSequencer IP reset

Do you have an idea, why the PLL doesn't lock?
Many thanks for help in advance.

0 Kudos
5 Replies
CHebl
Beginner
105 Views

Further Info about IP Generation:
ATX PLL:

"Seperate Waitrequest and Status PreSICE" is enabled
CSR and Capability registers are enabled

Reset Controller:
pll_pd duration is 1 us
All other durations set to 70 us and automatic mode

CheePin_C_Intel
Employee
65 Views

Hi,


As I understand it, you have some inquiries related to the A10 ATX PLL dynamic reconfiguration. You seems to observe that after reconfiguration, your ATX PLL does not achieve lock. To facilitate further debugging, just would like to check with you on the following:


1. As I understand it, the ATX PLL support embedded streamer and multi profile dynamic reconfiguration. Just wonder if you have a chance to try with it.


2. Just wonder if you have had a chance to run a Modelsim simulation to verify the functional behavior? If not, it is recommended for your to create a simple test design using embedded streamer and multi profile. Then run through the Modelsim simulation.


Please let me know if there is any concern. Thank you.


CHebl
Beginner
43 Views

Hi @CheePin_C_Intel ,

 

sorry for answering this late.

The embedded Streamer isn't really an option, because I have lots of profiles I'd need to embedd.
I did a QuestaSim simulation though and found everything to work when reconfiguring the PLL manually.

There are some weird effects in the simulation though. I doublecheck all registervalues before and after PreCISE calibration and found, that all register values before calibration were as specified, while all registervalues after calibration changed (according to documentation are even incorrect (e.g. wrong counter values), even though the correct frequency appears). This doesn't happen in the real hardware, but then again the real hardware doesn't run correctly.

This leads me to the assumption, that maybe something with the CLKUSR is wrong. I set the "Device initialization clock source" to "CLKUSR Pin" in "Device and Pin Options" -> "General" and have a free-running 125 MHz clock connected to this pin. Do I need to take care of something additionally in HDL or assignment editor?

 

Edit: I found that in Arria V and Cyclone V channel bonding mode prohibits ATX PLL reconfiguration. While I didn't find the same in Arria 10 documentation I wonder if the ATX PLL behaves the same.

 

This is the registermap

Address Value pre calibraton Value post calibration Function
0x103 0x21 0xbf  
0x104 0x36 0x7f  
0x105 0x05 0x47  
0x106 0x32 0x3f  
0x107 0x00 0x3c N Counter
0x108 0x0b 0x7f L Counter
0x109 0x50 0xff M Counter
0x10a 0x04 0x7f  
0x10b 0x00 0xe1  
0x10c 0x01 0xff  
0x10d 0x00 0xff  
0x10e 0x00 0xff  
0x10f 0x00 0xff  
0x110 0x15 0x3d  
0x111 0x00 0x70  
0x11a 0x80 0xe0  
0x11b 0x00 0xc0  
0x11c 0x00 0xe0  
0x11d 0x00 0xe0  
0x11f 0x00 0x60  

 

CheePin_C_Intel
Employee
16 Views

Hi,


Sorry for the delay. Please see my response as following:


This leads me to the assumption, that maybe something with the CLKUSR is wrong. I set the "Device initialization clock source" to "CLKUSR Pin" in "Device and Pin Options" -> "General" and have a free-running 125 MHz clock connected to this pin. Do I need to take care of something additionally in HDL or assignment editor?

[CP] For your information, I am not sure about using the CLKUSR as device initialization clock source. Based on my understanding, on the board, we just need to supply a free-running and stable clock with the supported frequency to the CLKUSR pin. We do not need to add any additional assignment or setting in Quartus.


To further narrow down to reconfiguration related or recalibration related, it is recommended for your to do the following:


1. Create a simple test design ie with one channel Native PHY

2. Enable the embedded streamer and multi profiles features in Native PHY

3. Perform the reconfiguration using embedded streamer

4. Then perform ATX PLL calibration using your current method


If using embedded streamer + profile, you are still seeing similar problem, then we could further narrow down to recalibration. If using embedded streamer + profile and there is no problem, then we could narrow down to the reconfiguration steps.


Please let me know if there is any concern. Thank you. 



Best regards,

Chee Pin



CheePin_C_Intel
Employee
15 Views

Hi,


Regarding your observation of some of the register values change after calibration, for your information, the calibration process is expected to change some internal values. However, I am not sure which specific register values will be changed. Your observation would show that calibration has taken place.


Regarding the unsupported dynamic reconfiguration mode, you may refer to "Unsupported Features" section in the A10 XCVR PHY IP user guide for further details. You may cross check if the specific mode of yours fall under any of these.


Please let me know if there is any concern. Thank you. 



Best regards,

Chee Pin