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Hello.
I'm trying to implement 100G Ethernet
In Agilex™ 5 FPGAs: High-Speed Serial Interface (HSSI) Hard IP
documentation states that Agilex 5 supports these specifications - CAUI-10, XLAUI, XLPPI. But in the GTS PMA/FEC Direct PHY Intel FPGA IP IP core - I can't choose 10 transceiver lines, only 8.
I would like to use an external PHY to implement 100GE, but I don’t see a way to implement this in Agilex™ 5.
Assuming I implement the alignment, skew compensation, and bit ordering correctly (use 10 instance GTS IP Core)— would this be a feasible way to receive a CAUI-10 stream?
And if so — does it mean I could also implement CAUI-4 the same way (i.e. aggregating 4×25G manually), given that the transceivers can handle it individually?
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Hi,
As I understand your requirement is to implement CAUI-10 interface. If I understand it correctly it requires 10 lanes of transceivers, each operating at 100Gbps.
The Agilex 5 GTS XCVR lane cannot go beyond 28.1Gbps as per the datasheet, so how will it support 100Gbps/lane.
I guess mentioning CAUI-10 might be a typo in the datasheet or probably it only considers the Electrical Specification of it and not the functional spec. I will take an action to feedback this to the relevant teams to clarify this.
Regards
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Please ignore my previous comment. It is 10Gbps x 10 lanes.
I will check whether 10-lane bonding is possible or not.
Regards
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Hi,
The GTS User guide mentions restrictions related to bonding.
The GTS PMA/FEC Direct PHY IP only supports TX bonding. The IP does not support RX bonding. The IP supports TX bonding of x2, x4, x6, and x8 PMA channels for PMA direct mode and PCS direct mode.
Regards

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