Agilex 5 design using DDIO shows clock routing failures

[KKlei5]

I have a simple design, trying to control some output pins using the Agilex 5 and GPIO Intel FPGA IP.   The design is targeted for a new board design, but its so simple this could be done with the Agilex 5 DEV board.

I output a simple pattern, 4 GPIOs, with 2 different instances of the GPIO Intel FPGA IP, using different clocks, 100 mhz, and 100 mhz + 90 degrees out of phase.   When I attempt to build this design, Quartus fails with what appears to be a resource limitation on clock routing for the GPIO.   Its not really clear to me what this failure is indicating, or more importantly how to resolve it. 

Anyone understand this, or can point me to any Agilex 5 documentation indicating how this can be resolved?

Error (175001): The Fitter cannot place 1 DDIO_OUT, which is within Generic Component ddio_0.
Info (14596): Information about the failing component(s):
Info (175028): The DDIO_OUT name(s): hps|ddio_0|ddio_0|core|i_loop[0].altera_gpio_bit_i|out_path.out_path_fr.fr_out_data_ddio
Error (16234): No legal location could be found out of 503 considered location(s). Reasons why each location could not be used are summarized below:
Error (24403): The Quartus Prime Fitter cannot find routing connectivity from source hps|new_pll|new_pll|tennm_ph2_iopll on port O_OUT_CLK[0] to destination hps|ddio_0|ddio_0|core|i_loop[0].altera_gpio_bit_i|out_path.out_path_fr.fr_out_data_ddio on port CLK[0] because the routing resource is used by:
Error (24404): Source hps|new_pll|new_pll|tennm_ph2_iopll on port O_OUT_CLK[1] to destination hps|gpio_clk|gpio_clk|core|i_loop[3].altera_gpio_bit_i|out_path.out_path_fr.fr_out_data_ddio on port CLK[0].
Info (175029): 1 location affected
Info (175029): DDIOOUT_X148_Y0_N182
Error (175006): There is no routing connectivity between the DDIO_OUT and destination pin
Info (175027): Destination: pin q1_col_lv[0]
Info (175015): The I/O pad q1_col_lv[0] is constrained to the location PIN_CA31 due to: User Location Constraints (PIN_CA31)
Info (14709): The constrained I/O pad is contained within this pin
Error (175022): The DDIO_OUT could not be placed in any location to satisfy its connectivity requirements
Info (175021): The destination pin was placed in location pin containing PIN_CA31
Info (175029): 501 locations affected
Info (175029): DDIOOUT_X141_Y147_N74
Info (175029): DDIOOUT_X141_Y147_N101
Info (175029): DDIOOUT_X141_Y147_N182
Info (175029): DDIOOUT_X141_Y147_N209
Info (175029): DDIOOUT_X141_Y147_N236
Info (175029): DDIOOUT_X141_Y147_N263
Info (175029): DDIOOUT_X141_Y147_N290
Info (175029): DDIOOUT_X141_Y147_N317
Info (175029): DDIOOUT_X141_Y147_N344
Info (175029): DDIOOUT_X141_Y147_N371
Info (175029): DDIOOUT_X141_Y147_N128
Info (175029): DDIOOUT_X141_Y147_N155
Info (175029): and 489 more locations not displayed
Error (175006): There is no routing connectivity between the DDIO_OUT and destination I/O output buffer
Info (175027): Destination: I/O output buffer hps|ddio_0|ddio_0|core|i_loop[0].altera_gpio_bit_i|output_buffer.obuf_0
Error (175022): The DDIO_OUT could not be placed in any location to satisfy its connectivity requirements
Info (175021): The destination I/O output buffer was placed in location IOOBUF_X126_Y0_N338
Info (175029): 1 location affected
Info (175029): DDIOOUT_X148_Y0_N209

...

[sstrell]

Are you using the HPS?  It looks like you are.  How do you have the I/O peripherals set up in the HPS parameter editor?  It also looks like you've created pin assignments in the Pin Planner.  Is that where you've made DDIO assigments?

[KKlei5]

Yes, there is a HPS, but all pins used for DDIO are FPGA pins:

set_location_assignment PIN_CC19 -to a_n
set_location_assignment PIN_CF19 -to a
set_location_assignment PIN_CL6 -to b_n
set_location_assignment PIN_CK8 -to b
set_location_assignment PIN_BE50 -to c_n
set_location_assignment PIN_BF50 -to c
set_location_assignment PIN_BH41 -to d_n
set_location_assignment PIN_BH38 -to d
set_location_assignment PIN_CF22 -to q1_col_lv[3]
set_location_assignment PIN_CH22 -to q1_col_lv_n[3]
set_location_assignment PIN_CC22 -to q1_col_lv[2]
set_location_assignment PIN_CA22 -to q1_col_lv_n[2]
set_location_assignment PIN_CF28 -to q1_col_lv[1]
set_location_assignment PIN_CC28 -to q1_col_lv_n[1]
set_location_assignment PIN_CA31 -to q1_col_lv[0]
set_location_assignment PIN_CC31 -to q1_col_lv_n[0]

DDIO assignments are made with GPIO Intel FPGA IP.

[ShengN_Intel]

Hi,

Have you try with Advanced Fitter Settings:

Final Placement Optimizations Always

Fitter Aggressive Routability Optimizations Always

Physical Placement Effort Optimize for Routability

Optimization Mode: options under Routability

Use different seed. Different seed will have different routing and placement.

Thanks,

Regards,

Sheng

[ShengN_Intel]

Hi,

May I know do you have any further concern?

Thanks,

Regards,

Sheng

[KKlei5]

I don't have a clear answer yet, but I did get from Intel/Altera that the Agilex 5 has some limitations not present in previous CyclonV, Arria10 or Stratix10. 

Engineering confirmed the restriction of one single clock source for a byte/lane. This is a hardware restriction and needs to be followed. Given this, all the DDIOs located in a byte/lane should have only one clock source, even if they belong to another GPIO IP instantiation. I am waiting for feedback on the documentation part.

[ShengN_Intel]

Hi,

Understood that. You may open a new Premier Support ticket to track the documentation progress.

Thanks,

Regards,

Sheng