For Agilex I parts, the ones with just the F-Tile, the Product Table says: 32 Gbps (58 Gbps) / High-Speed Transceiver 58 Gbps (112 Gbps). Can you select from 32Gbps(58Gbps) AND 58 Gbps(112 Gbps), or is it an OR. For Example , in the 3343A package it says 64(48)/ 8(8). So can I have 64x 32 Gbps channels AND 8x 112 Gbps channels in my design?
The info is still very limited but below is what I managed to find out.
There are 2 types of transceiver architecture in F-tile.
- One type can support till max 32G (NRZ) or 58G (PAM4)
- The other type can support till max 58G (NRZ) or 112G (PAM4)
The actual count of usable transceiver channel in one FPGA is not finalized yet as it depends on user transceiver configuration setting and also the channel pin placement. Some resources are shared between different channel.
In future, there is plan to publish some guideline doc to help customer understand F-tile usage and pin placement guideline
Stay tune for it.
You may also want to consult your local FAE for latest info update on F-tile from time to time