core clk work in 250M Hz，read and write HBM2 no problem
if we change the work freq to 275M，the RW verification would be wrong. the test bench is self design prbs verify program，we found 2-5 error per test，the target would be 350M Hz
we found core clock is 370M Hz in ip userguide
If you refer to HBM2 user guide doc page 21 - core clock frequency explanation :
- The maximum supported core frequency depends on the device speed grade and timing closure of the core interface clock within the FPGA.
I am not sure where do you see the 370MHz spec but that most likely is theoretically max supported spec but it still depends on user design timing closure to determine the achievable Fmax.