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1SM21BHU2F53E2VG,客户在使用quartus pro 19.3
客户希望在一个 H tile的24个收发器中实现12个单独发送,每个发送速率都不一样,编译的时候发现发送模块好像都调用了HSSICR2REFCLKDIVIDER 这个东西 不知道是干什么用的
发现一个H tile里面24个收发器里只有8个这模块,如果要每路的发送时钟都是独立,做发送的时候能绕开这个模块吗 否则应该怎么做12个发送呢?
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HI,
I don't think I saw this "HSSICR2REFCLKDIVIDER" in the user guide doc
- https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/stratix-10/ug_stratix10_l_htile_xcvr_phy.pdf
May I know where do you see this block as I suspect it could be some internal block generated or process by Quartus in background processing ?
Typically what matter is the setting in the NativePHY IP.
- As long as user key in the correct setting in NativePHY IP as per their design requirement then it's fine.
- Quartus synthesis and fitter compilation will review the input setting from user and generate some internal processing in background.
- User doesn't need to care for these background processing by Quartus. These internal block are used for Quartus compilation process only and doesn't affect user design functionality.
Thanks.
Regards,
dlim
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HI,
I don't hear back from you after my feedback explanation.
Hopefully I clear your doubt.
For now, I am setting this case to closure.
Thanks.
Regards,
dlim

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