Agilex I series Hard EMIF for HPS cannot be fitted by fitter

[Hufei]

Dear friends,

I am trying to generate a programming file for Agilex I series device dev kit with CXL and PCIE support. But I got stuck at the fitter stage.

Quartus : Pro 21.3

Device name : AGIB027R29A1E2VR0

Error: 

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 ADDR_CMD_GRP(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.
Error(175020): The Fitter cannot place logic ADDR_CMD_GRP that is part of Generic Component HPSEMIF_SYSTEM_emif_fm_hps_0 in region (280, 333) to (281, 333), to which it is constrained, because there are no valid locations in the region for logic of this type.
Info(14596): Information about the failing component(s):
Info(175028): The ADDR_CMD_GRP name(s): emif_fm_hps_0|emif_fm_hps_0|arch|arch_inst|io_tiles_wrap_inst|io_tiles_inst|tile_gen[1].tile_ctrl_inst_ADDR_CMD_GRP_3
Error(16234): No legal location could be found out of 1 considered location(s). Reasons why each location could not be used are summarized below:
Error(175005): Could not find a location with: ADDR_CMDx3 (1 location affected)
Info(175029): ADDR_CMD_GRP containing J9
Info(175015): The I/O pad ddrt_if_mem_ck[0] is constrained to the location PIN_B29 due to: User Location Constraints (PIN_B29)
Info(14709): The constrained I/O pad is contained within a pin, which is contained within this ADDR_CMD_GRP

The bolded part seems to be the issue, some kind of conflict between user constrained IO assignment and other constraints.

The pin assignments are extracted from the schematic that comes along with the board. But somehow this wouldn't go through.

[sstrell]

Did you add your own pin assignment for location B29 for something?  The HPS uses a specific I/O bank for its EMIF interface, so if you put something else there, it would interfere.

[AnilErinch_A_Intel]

Hi Hufei,

Please let us know whether the issue got resolved based on the previous comments.

Any feedback will be appreciated.

Thanks and Regards

Anil