Altera DE2: LVDS bit alignment issue

[Altera_Forum]

I'm trying to verify whether my FPGA board (Altera DE2) can support LVDS. For this purpose, I set up a simple system to test it, using an ALTLVDS_TX module to output to a GPIO pair, which is then connected to an input GPIO pair and corresponding ALTLVDS_RX module. The data I'm transmitting is a simple 8-bit up counter, at 100 Mbps, nothing too speedy. However, I'm experiencing bit alignment issues, where the received bits are the same as the transmitted ones, but shifted. I wouldn't mind if the shift was by a multiple of 8, but right now it's by 21 bits, so my words are coming out corrupted. 

 here (https://imgur.com/a/7mune) are some waveforms and the circuit schematic  here's (https://imgur.com/a/0hwqa) the transmitter settings.  here's (https://imgur.com/a/rqsqt) the receiver settings.   The most obvious thing I tried to change is the phase alignment alignment of tx_in WRT tx_inclock, or rx_in WRT rx_inclock, but the only option I get is 0.

[Altera_Forum]

Your receiver doesn't know how to align itself to your incoming data. You need to control the receiver and tell it where to align itself to. 

 Have a look at the 'rx_data_align' port option in the ALTLVDS_RX Parameter Settings. See 'Table 10. ALTLVDS_RX Input and Output Ports' of the "lvds serdes transmitter/receiver ip cores user guide (https://www.altera.com/en_us/pdfs/literature/ug/ug_altlvds.pdf)".  If you're only sending the 8-bit counter value then you've nothing to look for to align to. You will need to frame your data with something your receiver logic can look for and then control the receiver's bit slip until you are aligned as required.  Cheers, Alex

[Altera_Forum]

Thank you for your reply. In my future intended use, the transmitter does not send any additional data for alignment. It does, however, provide a frame clock for this purpose. Do you think it can be of use?

[Altera_Forum]

Hi,  

 can you share ur project files.

[Altera_Forum]

You will need something against which you can frame the data. So, yes - perhaps a frame clock might work. However, I think you've already found that you hadn't predicted the alignment of the rx data. So sending a framing clock that is generated separately to the tx/rx IP will prove impossible to align to. The fact that the ALTLVDS_RX offers a bit slip option tells us that the alignment is not predictable. There's no telling at what point in the received stream the ALTLVDS_RX will even lock. So the alignment is unpredictable - hence the need for the bit slip circuitry. 

 I think you'll end up needing to add framing to the 8-bits of data you're carrying. You may only need to add one bit that's static and search for that.  Cheers, Alex