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Irrespective of the relative evil of gating clocks in FPGAs my understanding was that one should synchronize the enable signal to the clock being gated by means of a flip-flop chain.
However, while studying the documentation for the MAX10 device I stumbled over the following section: clock enable signals (https://www.altera.com/documentation/mcn1395213337540.html#mcn1395926825834) where the figures 5 and 6 seem to indicate that no synchronization seems to be necessary. https://i.stack.imgur.com/hffeq.png (https://i.stack.imgur.com/hffeq.png) https://i.stack.imgur.com/n5b4c.png (https://i.stack.imgur.com/n5b4c.png) Do I miss something? Moreover, how should I constrain a gated clock?Link Copied
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I understand that there are no two stage registers but I believe the document meant to gate the clock with enable (generated from its domain) as per figure 5
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