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Altera Modelsim problems

Altera_Forum
Honored Contributor II
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Hi All, 

 

I am a newcomer to VHDL having done a previous course using Verilog. I have a clock divider which produces one clock T-state-wide pulses from a 50Mhz system clock (say, every 10 milliseconds, every 50 milliseconds, etc). This is instantiated in a switch debounce entity that provides a little more than just a debounced switch pulse. This has compiled fine and produced sensible simulation results using Altera's simulation tool on Quartus v9.1. Then I created a simple test bench. I have used the native-link simulator stuff in Quartus by going to Assignments->EDA Tool Settings and filling in the Simulation card appropriately with the Altera Modelsim as the tool. The test bench entity is the top level and instantiates the switch debouncer entity as a DUT. Then I go to Processing->Start->Start Analysis and Elaboration. This works fine. Then Processing->Start->Start EDA Netlist Writer. Fine. Then Tools->Run EDA Simulation Tool->EDA Gate Level Simulation. All is well, it pulls in all the Cyclone II information from the project set up, brings up a waveform display in Modelsim, and puts signals and waves into it. And the outputs respond to the input stimulus with clock-to-output delays taken from the Altera data. So timing simulation is fine. But initially, especially if it was a more complicated design, I might want to just check out the functionality first by using Tools->Run EDA Simulation Tool->EDA RTL Simulation. This runs but here is the problem, or one of the problems. The waveforms are produced but there are no output responses to input stimulus. The clock is fine and the inputs follow their patterns in the test bench, but the outputs do nothing. So timing simulation works but RTL simulation doesn't. Why is this? Incidentally, Quartus shows an RTL schematic in Tools->Netlist Viewers->RTL Viewer which looks fine and in order. (I've had Verilog designs that weren't working that have produced RTL diagrams like plates of spaghetti, and rightly so!).  

 

The other problem is a string of warnings like this: 

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 2520 ns Iteration: 0 Instance: /swdb_tb/dut# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es).# Time: 2520 ns Iteration: 0 Instance: /swdb_tb/dut 

 

and so on up to the set run time of 15us. All the signals/inputs/outputs in the entities are standard_logic except for the counters which are standard_logic_vectors like this: 

 

SIGNAL Count : STD_LOGIC_VECTOR ((n-1) DOWNTO 0); 

 

n is declared earlier in the GENERIC section as a NATURAL := specified value. 

 

The specified value will be different depending on whether I've commented in or out a small value for testing or large value for real use. I understand that there are one or two ways of turning these warning messages off although the methods I've tried have not succeeded. On the other hand I would rather be warned if something isn't quite right and take steps to kill the problem at source.  

 

Can anyone throw any light on this? Thanks.
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Altera_Forum
Honored Contributor II
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Hi, 

Large block of text :-) 

 

--- Quote Start ---  

So timing simulation works but RTL simulation doesn't 

--- Quote End ---  

 

Verify time resolution. RTL simulation are usually in ps 

maybe other forumers have ideas. 

 

 

--- Quote Start ---  

# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es). 

# Time: 2520 ns Iteration: 0 Instance: /swdb_tb/dut 

--- Quote End ---  

 

It usually means that there are conflicts or undefined signals. And those signal are on one operand of your +,-,*,/ operations 

You try to make s <= a+b; with A = "uuuuuu1" for example. 

 

Nota Bene : std_logic are resolved type.
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Altera_Forum
Honored Contributor II
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Many thanks mmTsuchi. 

 

Sorry about large text block - just setting the scene.  

 

The resolution was set at 100ps. But from what you said I went and looked at my two counters (in the switch debounce module) and set their initial states as zero like this: 

 

SIGNAL Count : STD_LOGIC_VECTOR ((n-1) DOWNTO 0) := B"00"; 

SIGNAL Count2 : STD_LOGIC_VECTOR ((n2-1) DOWNTO 0) := B"0000"; 

 

Not elegant and there must be a better way of doing it. But, re-did the Processing->Start->Start Analysis and Elaboration, followed by a new EDA Netlist and then ran the RTL Simulation tool as before. And this time there were no warnings at all and all output signals were present and correct. Bang in sync with the clock of course because there is no timing information about the Cyclone chip (the one in my DE2 development board) but the RTL simulation worked. The 'n' values above are small because they are just for running simulations like this. They are 'naturals'.  

 

What would you say is the most elegant way of defining counters that can be used for timing or cycling operations like these and with count range definable using different generics to produce small counters for desktop simulation and large counters for real world use? Actually in my clock divider I used variables like this for my counter declarations: 

 

variable TenmsCntr : natural range 0 to 2**(n - 1) := 0; 

 

so perhaps that is what I should do for the debouncer. 

 

I never use counter outputs as clock signals of course. I always use the system clock for that. The clock divider for this design produces 20ns wide (1/50MHz) enable signals at 10ms intervals, 50ms intervals, 0.5 second intervals (for a clock colon) and 1 second intervals (for a microwave oven cook time down counter).  

 

Thanks again.
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Altera_Forum
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--- Quote Start ---  

SIGNAL Count : STD_LOGIC_VECTOR ((n-1) DOWNTO 0) := B"00"; 

SIGNAL Count2 : STD_LOGIC_VECTOR ((n2-1) DOWNTO 0) := B"0000"; 

 

Not elegant and there must be a better way of doing it 

--- Quote End ---  

 

SIGNAL Count : STD_LOGIC_VECTOR ((n-1) DOWNTO 0) := (others => '0'); SIGNAL Count2 : STD_LOGIC_VECTOR ((n2-1) DOWNTO 0) := (others => '0'); 

 

 

--- Quote Start ---  

variable TenmsCntr : natural range 0 to 2**(n - 1) := 0; 

--- Quote End ---  

 

warning : It means 0 to 128 if n=8. That is surely not what you want. 

You are making an error, you should write variable TenmsCntr : natural range 0 to (2**n) - 1 := 0; -- means 0 to 255 if n=8 

 

NB : You write too much. "Keep It Simple and St*pid" 

Happy to help you.
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Altera_Forum
Honored Contributor II
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Doh! I feel ashamed to have wrapped the wrong part up with my parantheses. After all these years.... 

 

Thanks
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