Altera PLL cascading

[Altera_Forum]

Hi. I'm using Cyclone V E. 

 I have 2 PLLs in project.  Can I use a pll cascading feature in this FPGA?  Why I can't just connect PLL's one output outclk0 with refclk of PLL two?  When I try to use connection cascade_out with adjpllin and remain refclk unconnected, I have an error 175001 in fitter.

[Altera_Forum]

In Error 175001 there should be some sub-messages which tells you more exact what your problem is. 

Please post this sub-messages here.

[Altera_Forum]

Errors: 

175001  177014  11179

[Altera_Forum]

Hmm, somewhere you're connecting something terribly wrong. Did you try this: 

https://www.alteraforum.com/forum/attachment.php?attachmentid=8608   I did a small testdesign and configured the PLLs like that and had no problems compiling it. Unfortunately I can't test it in hardware because I don't have a Cyclone V.

[Altera_Forum]

PS: For a good help you can also use this Link: 

http://quartushelp.altera.com/13.1/master.htm#mergedprojects/msgs/messlist_auto.htm  At least it gives you a little bit more Information about Warnings, Errors and so on. Just search for your Message-Number and follow the Link.

[Altera_Forum]

https://www.alteraforum.com/forum/attachment.php?attachmentid=8611 I have reproduced your testdesign with my device : 5CEBA4U15I7.  

 Also thank you for useful link with quartus errors and warnings!

[Altera_Forum]

You used fractional PLLs. I used Integer PLLs. 

 Perhaps this will help: (on page 22) http://www.altera.com/literature/hb/cyclone-v/cv_52004.pdf

[Altera_Forum]

OK, with your FPGA (5CEBA4U15I7) I get the same Errors even with Integer PLLs. Is this FPGA capable of using PLLs like that? 

Do you have a Datasheet?

[Altera_Forum]

I have the same question here: Why I can't just connect PLL's one output outclk0 with refclk of PLL two? Must I use the cascade_out & adjpllin? what is the difference? 

[Altera_Forum]

Just use one PLL and cascade its multiple outputs. See here https://www.youtube.com/watch?v=t4fwna3-gi8