Altera PLL timequest nets

[Altera_Forum]

Hello, 

 I have an Integer PLL instantiated in my Cyclone V SOC design. In Timequest, I noticed 2 possible nets to choose from for this PLL:  1. "FRACTIONAL_PLL_O_VCOPH0" 2. "outclk_wire[0]"  Which one is correct for an Integer PLL ?

[Altera_Forum]

I assume you are talking about creating a generated clock for the output of the PLL. Instead of doing that, just use derive_pll_clocks. That automatically creates all the clock constraints for all PLL outputs, assuming you've constrained the input reference clocks.

[Altera_Forum]

--- Quote Start ---  I assume you are talking about creating a generated clock for the output of the PLL. Instead of doing that, just use derive_pll_clocks. That automatically creates all the clock constraints for all PLL outputs, assuming you've constrained the input reference clocks.  --- Quote End ---   No. I used "derive_pll_clocks" and:  1. "FRACTIONAL_PLL_O_VCOPH0" 2. "outclk_wire[0]"  Are the names the tool gave to the PLL output clock.

[Altera_Forum]

The outclk_wire[0] would be the integer PLL output.

[Altera_Forum]

Is there any way to make Timequest name this clock after the HDL net name connected to it ?

[Altera_Forum]

Where in Timequest are you looking? Sure you're not talking about SignalTap?

[Altera_Forum]

Timequest -> Constraints tab -> Add input delay...

[Altera_Forum]

--- Quote Start ---  Is there any way to make Timequest name this clock after the HDL net name connected to it ?  --- Quote End ---    Unfortunately, no. That's the caveat for using derive_pll_clocks. If you want to give the derived clocks custom names to make them easier to recognize in reports and use in other constraints, generate an SDC report (or write out an SDC file with the -expand option enabled) to see the standard create_generated_clock commands for your PLL outputs. Then add the -name option to those constraints with the names you want to use.