Appropriate ADC for educational project?

[Altera_Forum]

Hello folks! 

 I'm a student of 'Network Systems and Data Communications' department in Greece and am doing my final project/dissertation right now in Leiria, Portugal at Electrical Engineering department.  Because the subject is kind of complex, I'm going to introduce to you only the part on which I'd like to set my specific question.  I want to implement a small device/circuit which will be inputted some analog voice commands from a normal electret mic. Till now I'm not clear about what pre-amp/op-amp I should use, but I believe I'll figure this out.  The implemented circuit will be interfaced onto a Pluto-II (Cyclone-I) FPGA board, probably SPI/i2c will fit the best. I've read a lot about ADC's appropriate for voice/audio systems, and I suggest that an Σ-Δ (sigma-delta) ADC will be good for me, in combination of a simple low-pass anti-aliasing filter consisting of a resistor and a capacitor in parallel before the ADC.  Actually, regarding the Σ-Δ ADC I still have no clear image if it is a linear or logarithmic ADC, cause as far as I know, it should be a logarithmic one for audio sampling, isn't it?  Considering a specific topic of your forum and obvious knowledge you people got, I thought that maybe you could suggest to me any appropriate market ADC for my purpose.  Thank you!  Sincerely, David

[Altera_Forum]

Nonlinear coded AD/DA has been used in early days of digital voice processing (e.g. with the µ-law codec), but it's long gone. SD ADC are linear by it's operation principle, also any kind of digital signal processing (e.g. decimation, filtering, FFT) is based on linear coding. If huge dynamic is involved in an application, it may use dynamical gain switching and a respective floating point data representation. But it's surely not required for voice processing. I would assume, that a resolution of 10 or 12 Bit is sufficient for your purpose.

[Altera_Forum]

Try ADS1202 It works great and is small. 

Greetings to Leiria, from a Portuguese living in Germany.

[Altera_Forum]

Fvm, thank you for your reply! 

I'm sorry of not mentioning the bit-resolution I've thought about, but I was actually also considering of using a 12-bit resolution ADC. Thank you anyway!  amilcar, what nice coincidence! I checked out the ADC you recommended, and it looks good to me!  Just a few things to clear out...  I saw that I can use an external CLK in mode 3 of ads1202 for application requirements, so that I can synchronize the data output with the fpga. That's important to me because I need to transmit data from the fpga via 10Base-T Ethernet which needs 20 MHz of minimum bandwidth. Is that right?  Also, due to oversampling of the device and the integrated DSP I won't need any further low-pass filter, is that so?  Finally, I thought of using NE5532 pre-amp as an op-amp. Will this work together properly?  Thank you all for your time!

[Altera_Forum]

Yes, you can send 20MHz clk to the ADC, but that ADC will send you a clk signal back, and you need to use that one to clock the data in. 

You can and should build the low pass filter together with the decimation of the delta-sigma. And the best way to achieve that on an FPGA is to implement the sinc3 filter described in the application notes of that chip. I can send you the code if you want. I have no experience with the NE5532.

[Altera_Forum]

Dear amilcar, 

 I'd firstly like to introduce myself: My name's David and I'm actually Austrian, having grown up in Greece.  It obviously seems like I got to make some experience with the filtering part, as I've not dealt enough with it.  I'd appreciate if you could send me the code for the sinc^3 filter, so I can start from somewhere.  Also, I didn't exactly understand the role of decimation of the delta-sigma?! Anyway I'll check out that stuff!  We can also speak German if you want, but I'd prefer English because of terminology! :-)  Thank you very much for your interest!  Sincerely, David

[Altera_Forum]

I just interestingly noticed that the input range of ads1202 is -250mV to 250mV, is that okay for voice processing? So that would be nice because I'd get rid of some noise amplifying the mic's signal less than expected.

[Altera_Forum]

--- Quote Start ---  Also, I didn't exactly understand the role of decimation of the delta-sigma?!  --- Quote End ---   ADS1202 is special in so far as it's only a SD modulator rather than a complete SD ADC. The latter would include the decimation function and output parallel data at the specified rate. The ADS1202 sends a bit bit stream at the SD oversampling frequency and needs external decimation to work as a full-featured ADC. The main reason, why the ADS1202 has been designed this way is because it's intended for operation through a isolated serial interface. But it's also a versatile building block for a FPGA analog front end.  You should refer to the basic SD converter theory, if you are interested to learn more about the role of decimation in SD operation, particularly noise shaping. But I think, the ADS1202 applications give some insights. A sinc^x filter (CIC decimator is just another word for it) hasn't a steep characteristic. If you decimate voice data to a moderate sampling frequency (e.g. 8 to 16 kHz) with this filter, high frequent signal components would be attenuated considerably, you may want to add either a correction filter or use a decimator with different characteristic in the final step of a multi stage decimator design.

[Altera_Forum]

--- Quote Start ---  I just interestingly noticed that the input range of ads1202 is -250mV to 250mV, is that okay for voice processing? So that would be nice because I'd get rid of some noise amplifying the mic's signal less than expected.  --- Quote End ---    About the Input Voltage i haven't got that. How much voltage it should be inputted? I am not so experienced but the Datasheet says that the  Analog Input Voltage Range ......................... GND – 0.4V to VDD + 0.3V Vdd=+5v Gnd= 0v  And at the specs it has this Vin. +In = –250mV to 250mV  Can anyone explain me because i am a little confused, which voltage should i input!!!?  FvM thank you for your help but some of your answers are hard to understand because your knowledge is by farrr better that ours!!!!  Regards Giannis

[Altera_Forum]

Amilcar, 

 could you please send me your email, because I'm not able to send any PM yet.  I got some further questions regarding the adc you recommended me!  Thanks in advance!

[Altera_Forum]

--- Quote Start ---  Can anyone explain me because i am a little confused, which voltage should i input!!!?  --- Quote End ---   The first specification is from absolute maximum ratings, this voltage can be applied without damage. For correct ADC operation, both common mode and differential input voltage specification have to be kept. +/-250 mV differential input voltage is the nominal range.

[Altera_Forum]

Thank you very much!! It was very helpful. We have a very good waveform of 300-500 mV Peak-to-peak.... i think it will work properly. 

 The next wondering is about sigma-delta adc and the vhdl code we have to implement on the FPGA. Is there any book, referense which will help us at any level?  thank you again!!!!

[Altera_Forum]

The ADS1202 application notes (for motor control) have VHDL code on how to interface with it.

[Altera_Forum]

hmm ok, i need for my project an audio AD converter and you told my friend refugee that this ads1202 it can work for our purpose because it is a Sigma-Delta AD. 

 1.Can we use it for this application? 2.I have seen the VHDL code but i can understand it very good, can i find a book about that? 3.Is there anyother ADS which is better for Audio Convertion?  Thank you very much for your time!!! We are realy appreciate your help!!

[Altera_Forum]

1. Basically, yes. With the questioned resolution, not for a CD audio quality. 

2. A good explanation of decimation and other basic topics of signal processing is in U. Meyer-Baese, digital signal processing with fpga. It's often refering to Altera tools and FPGA. And the classical paper of the CIC inventor Hogenauer, EB, "An Economical Class of Digital Filters for Decimation and Interpolation," IEEE Transactions  on Acoustics, Speech and Signal Processing, ASSP-29(2): pp. 155-162, 1981 3. The most versatile audio converter covering the range from low rate to CD audio would be a programmable codec as utilized in many Altera and Terasic Dev Kits. It already includes decimation with an appropriate steep filter and outputs a serial audio data stream.

[Altera_Forum]

I recomended the ADS1202 because you can trade-off resolution with data-rate, and it has the nice effect of shaping the SNR by pushing noise into the higher frequencies. 

 BUT..... there night be others out there that are even better for audio applications.

[Altera_Forum]

Dear Amilcar, 

 On the Verilog Code tou sent to David,   at the Declaration,    --- Quote Start ---  input wire clk, // the main FPGA clk (its faster than the ADS1204 clk) input wire reset, // async reset input wire i_ds_clk_out, // the ADS1204 clk (derived from the main clk) input wire i_ds_out, // DS modulated output bit output reg signed [ADS1204::ENOB(DECIMATION)-0:0] o_result, // one extra bit for the sign output reg o_valid = 1'b0); // the result is new and valid  --- Quote End ---    In our application we want to encapsulate on the payload of UDP packets,  so we will fill a buffer with the words from the ADC,  1. the " o_result" contains a word of how many bits? and  2. on how many clock cycles i will have one word?  Also i want more than 12bits resolution for this audio application so what Decimation M number i will use?  Sorry for asking all these but im Still confused!!!  Thank you again!!!! Greetings From Beautiful Leiria!!!!

[Altera_Forum]

On the top of the file you can see the function that converts Decimation in EffectiveNumberOfBits (ENOB) . 

 By changing the decimation you get different bitwidths.  If decimation = 1 you get one word per clk cycle (bad performace because the word is 1 bit) If i.e. decimation = 32 you get one word every 32th clk cycle.  Hope this helps.

[Altera_Forum]

Yep you helped me a lot, 

 One more thing.. How many bits are the MSB? It depends on the Decimation ratio?

[Altera_Forum]

Which MSB ?

[Altera_Forum]

I am sorry, i meant how many bits will be the Word - o_result if the Decimation will be 512? 

It will be 16bits?  Thank you!!!