CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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I have an IOPLL in my design with the associated reconfig block. I am able to reconfigure the counters associated with clock output 0 and see that reflected in the clock 0 output frequency. I am not able to do the same for other outputs of the same PLL. The divide values on the other outputs seem to be stuck at there initial values even though I am able to read back the new values that I have configured them to.
