I was trying a rocketboard design in quartus and I am encountering a lot of warnings(during Analysis,Fitter and Timing estimate) in the compilation process. Are the warnings safe to ignore and still expect my design to work without any issue on board(FPGA).My aim is actually to use this example of rocketboard as a reference and achieve my design by making minor modifications. So can I expect my design to work without any performance violation on board with these warnings still present or should I resolve them in all cases?
It depends what the warnings are (and unfortunately, Altera IP can throw up 1000s of warnings).Warnings range from unused code in design files to whole blocks of logic being removed from the design because you forgot to connect something. The first set of warnings would be safe to ignore and design will work, but with the second one the design definitely wont work (as logic will be missing). Because Quartus can swamp you with warnings, my usual flow would be to assume Ive got it correct and then browse the warnings for tell-tale problems (logic removed etc) when it doesnt work. If the HDL code is all yours, then its easy to clear up the warnings. But usually you have altera IP in there, so clearing them just wont be possible.
Also - some designers deliberately write code that allows the synthesisor to throw logic away. This may be for easy of code readability, re-use or configurability. Either way, clearing up warnings in FPGA designs is practically impossible
Thanks Tricky for the immediate response.Most of the design part will be Altera IP and only I have added a top file to the design and used custom logic in there. No warnings are present for the file which I have created. All the warnings which I encounter are with PCIe hard IP. Any idea on how these can be minimised? They are leading to unconstrained paths in timing due to the warnings.
Let me cross check on that part once again as I used the sdc files of rocketboard with altered names.My warning reads something like this: Warning (332060): Node:top|inst|altera_pcie_a10_hip_161_xfln4sipcie_a10_hip_1|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|phy_g3x8:g_xcvr.g_phy_g3x8.phy_g3x8|altera_xcvr_native_a10_161_vhre4dyhy_g3x8|twentynm_xcvr_native:g_xcvr_native_insts.twentynm_xcvr_native_inst|twentynm_xcvr_native_rev_20nm2:twentynm_xcvr_native_inst|twentynm_pcs_rev_20nm2:inst_twentynm_pcs|gen_twentynm_hssi_8g_rx_pcs.inst_twentynm_hssi_8g_rx_pcs~byte_deserializer_pcs_clk_div_by_2_txclk_reg.reg was determined to be a clock but was found without an associated clock assignment.
Yes, thats a warning from timing analysis, not from the design itself.If you altered the names of the paths in the sdc file - is it possible you got the paths wrong, or you have forgotten some command like derive_pll_clocks from the sdc file?
Now I don't have issues with the altered path as I have taken the path from the STA report generated. I have used derive_pll_clocks but even then the timing issue is present. Now when I was going through other warnings, I got the below one. Can this lead to my previously posted warning?* Warning (18708): ATX/FPLL < top|inst|altera_pcie_a10_hip_161_ivbokga : pcie_a10_hip_0|altpcie_a10_hip_pipen1b:altpcie_a10_hip_pipen1b|altpcie_a10_hip_pllnphy:g_xcvr.altpcie_a10_hip_pllnphy|lcpll_g3xn:g_pll.g_pll_g3n.lcpll_g3xn|altera_xcvr_atx_pll_a10_161_ekr4poq:lcpll_g3xn|a10_xcvr_atx_pll:a10_xcvr_atx_pll_inst|twentynm_atx_pll_inst > is not placed in the same bank as the reference clock. To which pin is this warning referring to? I am unable to locate it from the messages. i have multiple instances of PCIe and i get same warning for each. So is this something to do with pin assignment of PCIE refclk? *Sorry couldn't disable the smileys appearing so had to give spaces in between
I have got a better view on the issue now. The warning which I have posted above (both the warnings) occurs only if my PCIe is gen3x4 RP. When it is gen2x4 RP(rocketboard design) none of these are present.RP - root port Is there something additional to be constrained when i change my pcie from gen2 to gen3?
I have got a reply from Altera that these warnings exist for PCIe hard ip in 126.96.36.199 (can be ignored safely) and have been resolved in quartus version 17.0. Thanks Tricky for your response.