Aria V Display Port core sometimes disconnected

[relsaar]

Hi All

We have a PCB board we designed with AMD 8860 GPU that sends DP video to Aria V Display Port core (Qsys). In some of our boards we sometimes have DP connection issues.

The video signal goes to altera_xcvr_native_av and when RX is out of lock we see multiple retries on the DP AUX channel.

We came across this bug:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2019/why-does-the-intel--displayport-receiver-ip-with--enable-gpu-con.html

in our case the enable GPU is not checked.

Can anyone confirm this issue is also applicable to Aria V Display Port?

Thanks

Ariel

[Ariel1]

Hi, 

I'm trying to migrate from our 5AGXMA1D4F27I5 and I get only two options in the Quartus ->migration device: 5AGXMA3D4F27I5 or 5AGXMA3D4F27C5 (both parts have no stock available)

Can I assemble another Arria V with different embedded hard IP? (see page 6#) I can migrate to 5AGXBA3D4F27C4N or 5AGXFA3D4F27C4N? 
Can I compromize on Transceiver Count# or Transceiver Speed Grade and still run the example design successfuly on my board that was designed for 5AGXMA1D4F27I5?

Thanks

Ariel 

[Ariel1]

Hi,

I created a spread sheet with all arria V with the similar package code and package type that can potentially host the design example on my board. Can you please help me filter out all the appropreate candidates PLDs?

Thanks

Ariel Saar

[Deshi_Intel]

Hi,

FPGA ALM is insides FPGA core logic. Hard periphery IP like transceiver channel count won't matter to it.

So, you want to either

• (A) try out bigger AV FPGA with higher ALM count
  • Looking at the excel file is not safe.
  • It's better for you to change the example design AV device OPN and test out fitter compilation directly.
• or (B) check to see if you can reduce some feature in DisplayPort IP to reduce the ALM usage in your existing AV FPGA
  • I know reducing bit per colour definitely helps
  • You can also check to see if "support CTS test automation" setting is enabled in DP IP. Just disable it and regenerate IP again.

Thanks.

Regards,

dlim

[Deshi_Intel]

HI,

Just to follow up what's the latest status update ?

Did you manage to port over the example design to run some testing ?

Thanks.

Regards,

dlim

[Ariel1]

Hi,
I managed to compile the example design with minimal changes successfully but unfortunately our pld is too small.
I ordered a bigger arria V and as soon as ill get it I plan to assemble it and test the BER.
Thanks
Ariel

[Deshi_Intel]

Hi,

Thanks for the update.

In this case, may I suggest for case closure first as I can't let the case idle without activity update for too long ?

• Once you get your new FPGA and rerun hardware testing, then you can file new forum post to Intel to resume debug support discussion.
• Just tag the forum title with something like "continuous support from previous AV DP case 04894952" then the case will be routed to me to continue to help you up.

Thanks for your understanding.

Regards,

dlim

[Ariel1]

Hi,

OK - please close the case and I'll open a new one as you suggested.

Thnaks for your support.

Ariel Saar

[Deshi_Intel]

HI,

Thanks for your understanding

Alright, I will proceed to close this case first.

Regards,

dlim

[Ariel1]

Hi

Since our 5AGXMA1D4F27I5N is too small to host Intel example design we purchased 5AGXMA3D4F27C5N and assembled it on our board.

According to the migration design guide it supposed to be direct replacment however auto detect failed on reading devise ID.

I'm going to validate power, clk and jtag signals of the new PLD devise however can you please help me verify no schematice change is required after such migrating?  

Thanks

Ariel