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Arria 10: Booting U-Boot from SD-Card does not configure FPGA

LFrin
New Contributor I
4,958 Views

Hello,

 

I have adapted the example for the Arria 10 SOCDK (Arria 10 SoC - Boot from SD Card) to the HAN-Pilot-Platform evaluation board from Terasic. I used the make_sdimage_p3.py script to generate the SD-Card image without linux binaries:

 

Partition 3: (format raw, type 0xA2) - u-boot-splx4.sfp
Partition 1: (format fat) - sdfs folder with - fit_spl_fpga.itb and u-boot.img
Partition 2: (format ext3) - empty

 

The SOC start-up seems to be ok, but the FPGA does not get configured:

Boot Console Arria 10 SOCBoot Console Arria 10 SOC

 

When i start the board without SD-Card, put it in, and then connect with the debugger and start the system with the Debugging U-Boot script. The system boots and the FPGA gets configured…

The start-up runs like from SD-Card, but the FPGA gets configured!

 

Some more informations:

  1. Quartus (22.3 Pro) compilation with “Early Release of HPS IO”
    1.1 Qsys EMIF with enabled “Early Release Mode”

  2. Convert .sof to .rbf with: quartus_cpf.exe --convert --hps -o bitstream_compression=off golden_top.sof golden_top.rbf

  3. Make fit_fpga_spl.itb with fit_fpga_spl.its in \u-boot-socfpga\board\altera\arria10-socdk

I recompiled U-Boot with #define DEBUG in include\configs\socfpga_common.h and found these error:


No configuration specified, trying default…
Found default configuration: ‘config-1’
FPGA: FPGA node count: 2
FPGA: fpga-periph-1
FPGA: fpga-core-1
FPGA: Start to program core bitstream …
FPGA: Data offset was found.
Can’t get ‘load’ property from FIT 0xffe24ec0, node: offset 248, name fpga-core-1 (FDT_ERR_NOTFOUND)
FPGA: No loadable was found.
FPGA: Using default DDR load address: 0x400 .
FPGA: External data: offset = 0x582d4, size = 0x1dcfb44.
blk_find_device: if_type=6, devnum=0: dwmmc0@ff808000.blk, 6, 0

 

Does anyone have any idea what the problem could be?

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1 Solution
LFrin
New Contributor I
4,306 Views

Hi @aikeu,

okay, now im sure: The Intel In-System Sources and Probes IP hinders the FPGA from starting normally after it has been correctly configured by SD-Card. Even the old Quartus-Project works without the ISSP-IP. Now it makes sense why the FPGA starts when a connection to the programmer is established via JTAG or similar.

My workaround will be, that i only use FPGA Firmware without the debugging features (ISSP, SignalTap, ...) on the SD-Card and when i need this debugging features i will start the HPS with the ARMD DS debugger.

Thanks for the help, my problem has been solved.

Regards,

LFrin

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22 Replies
aikeu
Employee
4,467 Views

Hi LFrin,


Try to run with the pre-build binary and check if there is any error.

Can follow this document in the section (Running GSRD with Pre-Built Binaries) to test and see.

https://www.rocketboards.org/foswiki/Documentation/Arria10SoCGSRD


Thanks.

Regards,

Aik Eu


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LFrin
New Contributor I
4,456 Views

Hi @aikeu,

I only have the evaluation board Han-Pilot-Platform from Terasic and not the Arria 10 SoC Development Kit.

I don't think I can use the pre-made sd-card image from the link, or am I wrong?

I load the Terasic prebuild Image Linux LXDE Desktop (Kernel 4.9.78-ltsi) to my SD-Card and the configuration of the FPGA worked as expected:

 

Boot Console Arria 10 SoC Terasic Prebuild SD-CardBoot Console Arria 10 SoC Terasic Prebuild SD-Card

They used the old boot-flow in their reference designs, but i need to use the new U-Boot flow, because I want to start the new development with a current Quartus version.

I am running out of ideas why the FPGA is not configured when booting directly from the SD card, but it works when I use the debugger.

 

 

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aikeu
Employee
4,438 Views

Hi LFrin,


I think the pre-made one can work, try to checkout and see.

You mentioned that you wanto use the new building boot loader flow? The flow will be the same for all Arria10 family devices


Thanks.

Regards,

Aik Eu


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LFrin
New Contributor I
4,423 Views

Hi @aikeu,

Unfortunately, the pre-made SD card you mention does not work. U-Boot starts booting but then gets stuck:

 

Boot Console Arria 10 SOC Intel SoCDK Preebuild SD-CardBoot Console Arria 10 SOC Intel SoCDK Preebuild SD-Card

 

 

 

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LFrin
New Contributor I
4,432 Views

Hi @aikeu,

>> You mentioned that you wanto use the new building boot loader flow? The flow will be the same for all Arria10 family devices

I meant that the example project from Terasic was built with Quartus 18.1 and the SOC EDS and I work with 22.3 and U-Boot.

 

>> I think the pre-made one can work, try to checkout and see.

I will try this and then report back.

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aikeu
Employee
4,376 Views

Hi LFrin,


Seems that it stucked at trying to perform DDRCAL, it will shows DDRCAL failure after some time if I am correct.

Maybe as you mentioned the pre-built sd image not fully suitable. Anyway can make sure that the SW5 MSEL of your board is already configured to boot from sd card, refering to the HAN Pilot Platform Hardware Manual?


Thanks.

Regards,

Aik Eu


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LFrin
New Contributor I
4,368 Views

Hi @aikeu,

The SW5 (MSEL) Dipswitch is switched to 000 - FPP Mode - FPGA boot from Micro SD Card. I can boot the sample SD-Card-Image provided by Terasic and the FPGA is configured.

Unfortunately the configuration of the FPGA does not work when I use this and this guide to create U-Boot device settings (suitable for HAN-Pilot-Platform) myself to create an SD card image.

The Secondary Program Loader (SPL) and U-Boot are booting without any problems, the DDR memory is calibrated and I get into the U-Boot console. The only thing that does not work is the configuration of the FPGA.

Is it possible that by using the ARM-Development-Studio-Debugger, the .itb file, where the FPGA firmware is stored on the SD card, is loaded differently? I find it extremely strange that it works when I start the boot process using the debugger.

Is there another way to debug the programming process of the FPGA?

Are there any special requirements for the HPS2FPGA bridge if you want to configure the FPGA via the HPS?

 

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LFrin
New Contributor I
4,283 Views

The problem also exists when I work without "HPS early release of HPS IO". I convert the *.rbf file with the attached script and create my SD-Card as usual. The process hangs at "FPGA: Start to program peripheral/full bitstream ...".

I also found that it is enough to connect the ARM DS debugger, stop the ARM and reset it so that the FPGA is configured correctly.

The ARM loads from the SD-Card: SPL and U-Boot load correctly, FPGA is not configured. I connect to the ARM DS debugger and run the following script:

# initialize system
stop
wait 5s
reset
stop
wait 5s

FPGA is configured correctly.

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aikeu
Employee
4,276 Views

 

Hi LFrin,

Can check if the below has been enabled for your early IO release build?

To follow the new build flow referring to Appendix - Reducing Arria 10 Fabric Configuration Time ( https://www.rocketboards.org/foswiki/Documentation/BuildingBootloaderCycloneVAndArria10#Appendix_45_Reducing_Arria_10_Fabric_Configuration_Time ), the below items should be checked.

temp42.PNG

 

temp43.PNG

Thanks.

Regards,

Aik Eu

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LFrin
New Contributor I
4,264 Views

Hi @aikeu,

yes both items are checked for the early io build (i worked with this manual).

 

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LFrin
New Contributor I
4,236 Views

Hi,

Okay, I found something strange. I think that the FPGA is programmed correctly, but does not start.

As soon as I do anything on the JTAG interface after booting my custom U-Boot SD-Card (Quartus-Programmer-Autodetect/ARM-DS-Debugger/Insert external USB-Blaster/...) the FPGA starts running normally.

The board has an on-board USB-Blaster-II, I'm afraid this somehow prevents the FPGA from starting. However, I have no idea why and especially I do not know why the supplied SD-Card-Image works without this problem.

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aikeu
Employee
4,166 Views

Hi LFrin,


Do you mean if the FPGA image is packaged together with U-boot images into the sd-image, then there will be problem with the FPGA configuration during system sd-card boot up?


Thanks.

Regards,

Aik Eu


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LFrin
New Contributor I
4,131 Views

Hi @aikeu,

yes.

I packed the SD-Card like i wrote in the first post:

 

I have adapted the example for the Arria 10 SOCDK (Arria 10 SoC - Boot from SD Card) to the HAN-Pilot-Platform evaluation board from Terasic. I used the make_sdimage_p3.py script to generate the SD-Card image without linux binaries:

 

Partition 3: (format raw, type 0xA2) - u-boot-splx4.sfp
Partition 1: (format fat) - sdfs folder with - fit_spl_fpga.itb and u-boot.img
Partition 2: (format ext3) - empty

 

First I thought the SD-Card is booting normally, but the FPGA is not configured.

Then I noticed that when I do a reset using ARM-DS-Debugger-Script (connect stop reset stop) the FPGA starts running, which means the FPGA is configured when booting from SD-Card, but it does not start running.

Then again I noticed that it doesn't need a reset executed with the ARM-DS-Debugger, but only an event on the JTAG bus like an auto-discover from the Quartus programmer to start running.

I have not analyzed this further. On the evaluation board I used (HAN-Pilot-Platform) there is an on-board USB-Blaster II and it seems that this prevents the FPGA from starting properly, but I can't explain why. Also, I don't know why the sample SD-Card created with Quartus-Prime 18.1 Standard works. So it could still have something to do with my FPGA design?

Is there anything special to consider in the FPGA design when working with the HPS (resets clocks etc.), besides the correct initialization of the HPS component and the emif?

Regards LFrin

 

 

 

 

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aikeu
Employee
4,092 Views

Hi LFrin,


Can try to troubleshoot with the pre-made image by changing the partition content with the ones that you have built?


  1. dd if=.sfp of=/dev/sdb3 bs=64K //this is to update just the A2 partition with the SPL 
  2. Update fit_spl_fpga.itb and u-boot.img 


At the mean time I am trying to consult further regarding your previous observations.


Thanks.

Regards,

Aik Eu


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LFrin
New Contributor I
4,074 Views

Hi @aikeu,

thank you for your efforts so far.

I tried to edit the prebuilt sd card as you wrote, unfortunately it did not help.

 

But I think I have found the error. I set up a completely new Quartus-Project with only:

1. Initialized the HPS-Component

2. Debounced the RESET-Button

3. Added a Heart-Beat-LED controlled by the FPGA

 

After compiling, I first created my SD-Card exactly as in the instructions (Arria 10 SoC - Boot from SD Card) without building a dedicated U-Boot-Target for the Han-Pilot-Platform. The FPGA was configured normally on boot and the LED started flashing (FPGA starts running).

Then i build my own dedicated U-Boot-Target for this board and the FPGA also is configured normally on boot and the LED started flashing (FPGA starts running).

I can exclude that the problem is related to the SD-Card and U-Boot/SPL, both seem to work fine. I think the problem is in my Quartus-Project or the Programming-File. I will now rebuild (component-by-component) my old Quartus-Project until my FPGA no longer starts runinng after booting the SD-Card. So I intend to find the problem.

 

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aikeu
Employee
4,030 Views

Hi LFrin,


Good that you managed to run a working example on on your side.

May I know any new findings from your side after you tried to seperate the components build in your project?


Thanks.

Regards,

Aik Eu


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LFrin
New Contributor I
4,015 Views

Hi @aikeu,

 

Of course, I can keep you updated. I have successfully put the following components into operation without affecting the SD-Card startup:

- Of course the Hard Processor System

- PCI-Express Hard-IP

- Nios V Soft-IP with I2C/GPIO/Timer/JTAG-Uart/Voltsense/Tempsense

- Transceiver Native PHY (for SFP+-Fiber-Module)/Reset Controller/ATX PLL

The only thing missing now is an "In-System Sources and Probes" IP, I think this IP could be the problem.

 

Unfortunately I won't get to work on this project this week. But I will get back to you at the beginning of the next week.

 

Thanks,

Regards,

LFrin

 

 

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aikeu
Employee
3,952 Views

Hi LFrin,


Thanks for your feedback. Looking forward to your new findings.


Regards,

Aik Eu


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aikeu
Employee
3,898 Views

Hi LFrin,


Do feedback to me once you got some update on this week.


Thanks.

Regards,

Aik Eu


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LFrin
New Contributor I
3,863 Views

Hi @aikeu,

my new Quartus project is now designed like the old one, except that I don't use an "In-System-Source-and-Probes" IP and a "Signal-Tap" instance. In the old project I used the ISSP-IP to reset the FPGA. It might be that the initial value is wrong when booting from SD card and the FPGA stays in reset.

 

I believe one of these two instances is causing this problem. Tomorrow I will integrate both into my new project and then see if the error occurs.

 

Regards, LFrin

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