Arria 10 EMIF pin names

[Jaka_Bac]

Hello,

Looking at the pin special functions for the EMIF the pins have names like:

DDR4 _0_1_2_3_C_A_2

DDR4 _0_1_2_3_L_A_2

DDR4 _0_1_2_3_NO_C_A_2

...

DDR4 part of the name is obvious and also the A2 part, but I would like to know what is the meaning of:

..._0_1_2_3_C_..

..._0_1_2_3_L_..

part of the name.

[sstrell]

Where are you seeing this?

[Jaka_Bac]

In Pin Planner, when looking at pin properties of a pin that can be used for the hard memory interface

[AdzimZM_Intel]

Hi,

Can you share some snapshots of the Pin Planner GUI that shows this pin properties?

What are you trying to get from this pin information? Maybe there is other way to achieve that.

Regards,

Adzim

[AdzimZM_Intel · Accepted solution]

Hi @Jaka_Bac 

I have done some study on this pin information.

Since this is Address/command function, this only applicable for address and command signals.

Below are the details about this pin information.

DDR4_0_1_2_3_C_A_2

DDR4_0_1_2_3_L_A_2

DDR4_0_1_2_3_NO_C_A_2

DDR4 is for the memory protocol.

0_1_2_3_C or 0_1_2_3_L or 0_1_2_3_NO_C are for the memory variant.

A_2 is memory signal.

For the memory variant, the 0_1_2_3 is the IO lane usage in the IO Bank.

If 0_1_2_3, then all 4 IO lanes are used for this memory.

If 0_1_2, then 3 IO lanes are used for this memory. which is means the IO lane 3 is not used for the Address and Command signal/group.

The C, L and NO_C are the memory format and topologies.

C here means for the stack up configuration type.

L is for LRDIMM memory topology.

NO_C is other than stack up and LRDIMM memory format. Can be component, UDIMM, SODIMM, RDIMM memory topology.

It may a bit confusing to make the pin placement based on this pin information.

The better option is to refer to Functional Pin Information document that can be downloaded from the Pin-Out Files website.

Link: https://www.intel.com/content/www/us/en/support/programmable/support-resources/devices/lit-dp.html#tab-blade-1-2

In that document, you can find the DDR4 Scheme 1 to 6 and other memory protocol as well.

It's showing the pin placement for the Address and Command signal. You can refer to this document when fitting the pin placement.

Based on the pin information from pin planner and document,

• C is matching to DDR4 Scheme 1 and 2
• L is matching to DDR4 Scheme 5 and 6
• NO_C is matching to DDR4 Scheme 3 and 4

Regards,

Adzim

[AdzimZM_Intel]

Hi @Jaka_Bac 

Do you have any further question in this thread?

Regards,

Adzim

[Jaka_Bac]

Thanks! No further questions. You explained everything very clearly

[AdzimZM_Intel]

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.