Arria 10 FPGA Unpowered State

[Indumathi]

Hi Team,

I am designing an Arria 10FPGA Board For USS 3.0 GEN2 10 G Interface. I am new to this FPGA Based Design as well as multiple processors in one board. Could you please guide me and answer the below questions.

FPGA --> Arria 10 

Part Number --> 10AX057N2F40E2SG

Current Design --> Arria 10's I/O are interfaced with other peripherals[Processor/FPGA] in the board am designing. [ In My Design Arria 10 FPGA is the main IC and it is interfaced with other SOC too].

Questions.

1. What will happen if the peripherals are turned on before the Main FPGA Boots up or supply is up?

2. Can the Other IC''s turn ON  when the FPGA in the Booting Process. [ Before it completely bootsup].

3. Does the Arria10 FPGA Support HOT Socket/ Hot Pluggable in the Transceiver Lines? 

4. Will the FPGA Get Damaged when I try to plug in or remove the Device from the Arria10 board while it's in a Powered off state.

5. Does Arria 10 Support HOT Plug /HOT SOCKET for USB 10G Applications? . 

[AminT_Intel]

Hello,

Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 L-tile and H-tile device transceiver pins do not support ‘Hot-Socketing.’ Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins.

We would advise not to do that in unpowered state. The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices.

Thank you.

Amin

[HBhat2]

Hi Amin,

"The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices."

Above statement is confusing with

"Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins." This statement is in the below link. "1.3.2. Transceiver Pin Guidance for Unpowered FPGA " page 14

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an692.pdf

Is it possible to correlate above statement with statement in an692?

With Regards,

HPB

[AminT_Intel]

Hello,

Yes. The first statement described the process during power-up and power-down while the second statement described about configuring for unpowered FPGA.

Thanks.