Arria 10 HPS, SPIM mapped to FPGA

[TomCarpenter]

I am trying to wire up a SPIM peripheral from the Arria 10 HPS to FPGA IO pins, and there is one point of confusion in the technical reference manual.

In Table 214, the naming of pins, there is an output enable for the MOSI line when using the peripheral as a master. The name of this signal is given as "spim_mosi_oe"

This matches the RTL signal names.

However in Figure 112, a different naming convention is used:

Could you confirm whether the output enable is active high as implied by the signal naming:

assign mosi = spim_mosi_oe ? spim_mosi_o : 1'bz;

Or active low (as in the diagram):

assign mosi = spim_mosi_oe ? 1'bz : spim_mosi_o;

[aikeu]

Hi TomCarpenter,

From the technical reference manual, referring to the signal data transfer diagram, ssi_oe_n will be active low when going to perform a tx operation.

Thanks.

Regards,

Aik Eu

[TomCarpenter · Accepted solution]

So my issue was actually a pin assignment rather than the output enable logic.

After a bit of testing, it would seem for the Arria 10 the diagram in the technical reference manual is wrong. The output enable is active high

Following the signal naming convention not the diagram. The output enable is active high:

assign mosi = spim_mosi_oe ? spim_mosi_o : 1'bz;

[aikeu]

Hi TomCarpenter,

Noted with the respond. I will inform and discuss the issue to the team regarding the matter.

Thanks.

Regards,

Aik Eu

[aikeu]

Hi TomCarpenter,

Since the issue has been resolve I will close the thread for now. I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thanks.

Regards,

Aik Eu