In our design we are using a Intel Arria 10 FPGA: 10AS066H4F34E3SG.
An external CRYSTAL OSCILLATOR (510BCB133M000CAG) is connected to PIN E23-E24, which ensures the input CLK for a DDR3 Memory (IS43TR16512B).
We have checked the Aria 10 datasheet to find requirements regarding the external CRYSTAL OSCILLATOR in terms of jitter, but we could find the information we were looking for.
An input jitter of 10 ps peak-to-peak is mentioned @ Table 55. in the datasheet, but we do not know what type of jitter is it (period jitter/TIE/cycle-to-cycle jitter).
Our CRYSTAL OSCILLATOR (510BCB133M000CAG) has a Period jitter (RMS) of 2.1 ps and Period jitter (Pk-Pk) 18 ps.
Could you send us the proper requirements regarding the external CRYSTAL OSCILLATOR for DDR3 Memory?
Could you also state whether the chosen crystal oscillator meets the requirements of Aria 10? What happens if this requirement is violated?
Thank you for your help!
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I'm Adzim, application engineer will assist you in this thread.
"An input jitter of 10 ps peak-to-peak is mentioned @ Table 55. in the datasheet, but we do not know what type of jitter is it (period jitter/TIE/cycle-to-cycle jitter)."
I've checked with internal team and they stated that the TIE(phase) Jitter spec for clock oscillator is not more than 10ps PK or the equivalent RMS jitter is 1.42ps at 10e-12 BER or 1.22ps at 10e-16 BER.
The Arria 10 SoC Devkit has used Si5338 programmable oscillator which is has phase jitter of 0.7ps RMS typ and it's still within the spec.
I think the crystal oscillator that you used is still within the spec as well because the phase jitter is at 0.8ps RMS typ.
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