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Arria 10 Transceiver Receiving Flipped/Reversed Data

sl113
Novice
256 Views

I'm running a very basic simulation to understand how the Arria 10 Transceiver PHY needs to be setup and configured to replace a Stratix V transceiver device since we're going to be replacing the Stratix V device with an Arria 10. In the sim, I'm connecting a 1 channel Stratix IV Transceiver (still in use in the system) to one of the 6 channels of the Arria 10 Transceiver. I've set up the Arria 10 Transceiver to be as close to the settings that were configured in the Stratix V but I'm receiving data incorrectly.

 

The Stratix IV transceiver word alignment settings are not configurable and are set to manual word alignment with 20 bits with the aligning word in hex being 0x5F0BC after 8B/10B encoding which should be 0xBC1C before 8B/10B encoding. In the Arria 10 device, I have setup the word alignment in "Synchronous State Machine" mode with the same 20-bit aligning word. I have a TX interface on both the Stratix IV and Arria 10 device which are continually sending 0xBC1C (which should later be encoded to 0x5F0BC) for this simple sim to see if I can get the RX to sync. The 0x0000BC1C data packet is received as expected on the Stratix IV side, but on the Arria 10 the receive data is 0xBC1C0000. Is there something I'm missing during transceiver setup? I've attached the Arria 10 settings to this post.

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1 Solution
sl113
Novice
202 Views

I ended up changing the word alignment to "bitslip" and created my own code to toggle the rx_bitslip input. It seems to be working.

View solution in original post

5 Replies
CheePin_C_Intel
Employee
240 Views

Hi,


As I understand it, you are interfacing the SIV XCVR and A10 XCVR. From your observation, it seems like the A10 received data is byte-swapped. You are sending 0x0000BC1C but the A10 received data is 0xBC1C0000. 


For your information, in the A10 XCVR channel, there is no byte ordering block. You would need to code your own byte ordering module in the core logic to find the right ordering and re-order the data if needed during initial link up.


Please let me know if there is any concern. Thank you.


sl113
Novice
229 Views

Hi,

 

Can you elaborate on how I'd do this? Can I keep the RX word alignment in "synchronous state machine" mode or do I have to change it to "manual" mode? Before, the byte ordering in the SIV and SV transceivers were embedded in the Receiver PCS. In this case, since I'm receiving 0xBC1C0000 instead of 0x0000BC1C, how would I configure/pad the data so I will get the right bits at rx_parallel_data?

 

sl113
Novice
203 Views

I ended up changing the word alignment to "bitslip" and created my own code to toggle the rx_bitslip input. It seems to be working.

View solution in original post

CheePin_C_Intel
Employee
150 Views

Hi,


Sorry for the delay. I have been out of office and just back to office.


Glad to hear that you have managed to find a workaround which resolve your problem.


Please let me know if there is any concern. Thank you.


CheePin_C_Intel
Employee
150 Views

Hi,


This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


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