Dear all experts
Arria 10AX066 device is used for the project.
2 of DDR are used to read & write data between NIOS & DDR
Target frequency is 600M & 700M that causes reference clock as 125M & 175M
Based on what I know about Arria10, it contains hard phy on chip which requires reference clock for each PHY
However, what if I want to use PLL internally to generate clock for each referece clock of DDR PHY, then takes that corresponding PLL clock to the outside of FPGA (assign pins to take those generated clock by PLL) for connecting to DDR PHY
Do you think it is possible?
When I open up the pin planner, there are two pairs of LVDS clk pin per each bank (3B 3C 3D 3E)
However, fitting was failed when I assigned some of them.
Can someone figure this issue?
if I can't assign pins for the generated clock by PLL to take them out, can you tell me the reason?
I appreciate any comment or help
Thank you
